From patchwork Thu Nov 28 10:59:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 180413 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp7357884ilf; Thu, 28 Nov 2019 03:00:46 -0800 (PST) X-Google-Smtp-Source: APXvYqxMQGKi1hhCCkq6apIjO+c4j1sOOiVYNcYODxz3+09CE4y3IxCBEttcLanM4PFPSaDTaZLH X-Received: by 2002:a05:6402:13d4:: with SMTP id a20mr37741271edx.105.1574938846386; Thu, 28 Nov 2019 03:00:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574938846; cv=none; d=google.com; s=arc-20160816; b=UpNr95A0krzbG75pSwc+FCZ7lGB1mPFTc94PSG7SvUw9qW+NZPb2ueQHdKC7TG4Bmq aslKfyjLOW9zrVYhObDzk7ewnReGlQcqoNsbzprc/DcNrtK2hkRcQ1K01zhT4VxRyx2q uqAVI4exowsCEiRwXRS2i5un6dIhFCe0OSzfYbrNBoJ5i/tQkBRRwZa/bLAJTLenh6P9 h/g/EFSkBjSEIOXEg+S9PB9a5LxgTLTzC4nqnyMmcjW4EP7i8lUSChimSKfVj93ce6c9 A8mK4AvX0q4WtNfRSA0Jcxr2AD24chmOTB24Mg3nc0CHg/ydfNDz+FUOqAQL6q+BsGTl ZCcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EOL7+ILAJKMK9C2xGDp+0K1qLoucOFWJ/CJCGCWfatY=; b=F/0dx8vMMQ+yjkj5wE5XcjYbWuTP/LbJxAkbstBZP7NpoLh1NeR8h397aAkxQYU+Y6 YtIPXoDz92tJDJsD1yeoRBocZ+v35QeyjYjaot/L3GvKsEoHEc1CFO04ZvImopDpfnur gZxn/s5kLs02MOJTWuC2eXUZExsWSMJ9OvD+4kqNfw7cnO9QC3CJb1Zf86yTBLRVw0E8 2uyTYO1HSKHkpxMRo8hPuCKm/v4wmyMYDBgztjyZZpKNCuPwExLeAuYTbuRMO5UGmNM9 gk95HNETllEuZbQSBogtPjTb8WSBX+oPfTfAi4k/SknRFbnGvzPl2MB5Xw6yqt0LEcVr v+Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mcmXDonJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i47si12736023eda.91.2019.11.28.03.00.46; Thu, 28 Nov 2019 03:00:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mcmXDonJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727239AbfK1LAn (ORCPT + 8 others); Thu, 28 Nov 2019 06:00:43 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59264 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727286AbfK1LAk (ORCPT ); Thu, 28 Nov 2019 06:00:40 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xASB0YJl099863; Thu, 28 Nov 2019 05:00:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1574938834; bh=EOL7+ILAJKMK9C2xGDp+0K1qLoucOFWJ/CJCGCWfatY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mcmXDonJ5NWH485ZKvPfhkaToVfvAYupKM6cmCiosdBInYMhrfRItfCbirdAoXapC oc8xqLz99UE0wea/xt/YG2q6ZekIiINME7RyDHI0FMpLsj1aV6Ml7pkKb39Uy3dZo/ wq+0hj4DLlBqfHLKgWB7bT8yttFQ2dkFgrPeYU7U= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xASB0Xea032273 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 28 Nov 2019 05:00:33 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 28 Nov 2019 05:00:33 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 28 Nov 2019 05:00:33 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xASAxgJS073287; Thu, 28 Nov 2019 05:00:30 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , Subject: [PATCH v6 14/17] dmaengine: ti: New driver for K3 UDMA - split#6: Kconfig and Makefile Date: Thu, 28 Nov 2019 12:59:42 +0200 Message-ID: <20191128105945.13071-15-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191128105945.13071-1-peter.ujfalusi@ti.com> References: <20191128105945.13071-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split patch for review containing: Kconfig and Makefile changes DMA driver for Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P) The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P is architected to facilitate the segmentation and reassembly of SoC DMA data structure compliant packets to/from smaller data blocks that are natively compatible with the specific requirements of each connected peripheral. Multiple Tx and Rx channels are provided within the DMA which allow multiple segmentation or reassembly operations to be ongoing. The DMA controller maintains state information for each of the channels which allows packet segmentation and reassembly operations to be time division multiplexed between channels in order to share the underlying DMA hardware. An external DMA scheduler is used to control the ordering and rate at which this multiplexing occurs for Transmit operations. The ordering and rate of Receive operations is indirectly controlled by the order in which blocks are pushed into the DMA on the Rx PSI-L interface. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet / TR mode) - MEM_TO_DEV (Packet / TR mode) - Cyclic (Packet / TR mode) - Metadata for descriptors Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/Kconfig | 13 +++++++++++++ drivers/dma/ti/Makefile | 1 + 2 files changed, 14 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 72f3d2728178..a096f0ec3998 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -34,6 +34,19 @@ config DMA_OMAP Enable support for the TI sDMA (System DMA or DMA4) controller. This DMA engine is found on OMAP and DRA7xx parts. +config TI_K3_UDMA + tristate "Texas Instruments UDMA support" + depends on ARCH_K3 || COMPILE_TEST + depends on TI_SCI_PROTOCOL + depends on TI_SCI_INTA_IRQCHIP + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select TI_K3_RINGACC + select TI_K3_PSIL + help + Enable support for the TI UDMA (Unified DMA) controller. This + DMA engine is used in AM65x. + config TI_K3_PSIL bool diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index f8d912ad7eaf..9d787f009195 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o +obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o k3-psil-am654.o k3-psil-j721e.o obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o