From patchwork Mon Jun 29 12:52:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 192006 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp3194681ilg; Mon, 29 Jun 2020 13:16:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxm1C0yYKGu/4U3PBkETJZ6P0E/a2NgV4CINfduQYYdY+p8xFX/LslpeyyfyEigKv/476cz X-Received: by 2002:a17:906:e294:: with SMTP id gg20mr14792644ejb.521.1593461768303; Mon, 29 Jun 2020 13:16:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593461768; cv=none; d=google.com; s=arc-20160816; b=NHXLaQMdPyOsd+bYLWZzn67MoHNG1LaqfAySXBi+oxuSmQejXSUTBNnialnsrYchJA OESMBnC4MtaaF6H7LL7g6dKmXtPRPvOsD35IXMl6cFpVRz3xiC4RBZMJkQuRDeZjIIgC 7qkAxSm0H2TItXm7xuCDpaw+frTBgEDCgryXOzaoeJ4KFnKiseNu0mK6Oa129w6x5rH9 ayJaqJ+j9OAs7TMDYrKhqvX+s3aLENcL7eUU3eiHAkkPrFTcmCp0Uc5n30agUupzMGON 0dL0HRRzjJhiSKQpBeqBtCXj3PX8LrTlhiqb7bJ9L3ywmeGnfCuQkocW1gJjQLvi2aEb Ahnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Zyt3wUw/sJh31lxjxUg6MRwKjJfwWEqPIU3SE6r/4o8=; b=hoehR0xAQrwtCxVIuKPDe/rOJUSYWxTmkai1IxK2wtwArH/ddZB4Zr+7eN4Ijy64Fs u5/p5l/pX8dguOKqgUfjCCXqxlnCK2ku4MKleMdK/6HvXFZ3+4e0nf14v9FyZAi8GvaV bNmkHu/qhn/RkGod1k8+M6QQbrrSCAdd/XBFnY4xwJ+hip20RCL+f1DA0jSgnltKqcE0 VRBj+An59YKJH2DmSsHrYfdlt8Fhp7Pxx7x7d+ySEcn9fxlJ08ELn3mZ1u/YQQHTKeQT s3LAXkikZ4S+4k8exQ5T6zpTWKoN9Ey41okWN+esZ1CtgIRN09+De10NyijKnvcCFbj4 CpIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cbq06d+q; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id nk2si421773ejb.695.2020.06.29.13.16.07; Mon, 29 Jun 2020 13:16:08 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cbq06d+q; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732820AbgF2UQF (ORCPT + 6 others); Mon, 29 Jun 2020 16:16:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51036 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730684AbgF2UQC (ORCPT ); Mon, 29 Jun 2020 16:16:02 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05TCrBkB030035; Mon, 29 Jun 2020 07:53:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593435191; bh=Zyt3wUw/sJh31lxjxUg6MRwKjJfwWEqPIU3SE6r/4o8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cbq06d+qKqqa/ofe2X6l6iy3tcxXip29NGLMVqtuew/fFa6q8WDhFTtebk4edHXzP dlcuy/OHSUjfE5P9ipLMgir1L/E4mPvMR4bdm7OzMGGS4TznwGO5I1LMQv1yTEHoqO cyHVm8DwWHnrO4ug6MmF9iVXBuQ8niKf0z3Cc3Fw= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05TCrBY8015276 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jun 2020 07:53:11 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 29 Jun 2020 07:53:10 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 29 Jun 2020 07:53:10 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05TCquh2015456; Mon, 29 Jun 2020 07:53:08 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros , Sekhar Nori Subject: [PATCH v4 5/6] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0 Date: Mon, 29 Jun 2020 15:52:53 +0300 Message-ID: <20200629125254.28754-6-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200629125254.28754-1-rogerq@ti.com> References: <20200629125254.28754-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org USB0 supports super-speed mode on the EVM. Enable that. On the EVM, USB0 uses SERDES3 for super-speed lane. Since USB0 is a type-C port, it needs to support lane swapping for cable flip support. This is provided using SERDES lane swap feature. Provide the Type-C cable orientation GPIO to the SERDES Wrapper driver. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- .../dts/ti/k3-j721e-common-proc-board.dts | 32 +++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 6df823aaa37c..3294b96ebba8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -60,6 +60,7 @@ main_usbss0_pins_default: main_usbss0_pins_default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; @@ -335,16 +336,43 @@ status = "disabled"; }; +&usb_serdes_mux { + idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , , ; +}; + +&serdes_wiz3 { + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; +}; + +&serdes3 { + serdes3_usb_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + }; +}; + &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; - ti,usb2-only; ti,vbus-divider; }; &usb0 { dr_mode = "otg"; - maximum-speed = "high-speed"; + maximum-speed = "super-speed"; + phys = <&serdes3_usb_link>; + phy-names = "cdns3,usb3-phy"; }; &usbss1 {