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[v4,6/6] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line

Message ID 20200629125254.28754-7-rogerq@ti.com
State Superseded
Headers show
Series arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support | expand

Commit Message

Roger Quadros June 29, 2020, 12:52 p.m. UTC 
The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT)
to debounce the CC lines in order to detect attach and plug orientation
and reflect the correct DIR status. [1]

On the EVM however we need to wait upto 700ms before sampling the
Type-C DIR line else we can get incorrect direction state.

[1] http://www.ti.com/lit/ds/symlink/tusb321.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>

Signed-off-by: Sekhar Nori <nsekhar@ti.com>

---
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 +
 1 file changed, 1 insertion(+)

-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 3294b96ebba8..6307fe5ccb06 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -350,6 +350,7 @@ 
 
 &serdes_wiz3 {
 	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
 };
 
 &serdes3 {