From patchwork Mon Oct 12 13:17:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317630 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616488ilm; Mon, 12 Oct 2020 06:19:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2Fc7tLvXFFQZ8pKdl43D6J44V1I0VoUCVdz9ctQAkQtbR6PlZZedsQw8+OfNtE6PKuFql X-Received: by 2002:a05:6402:3070:: with SMTP id bs16mr14464193edb.371.1602508779797; Mon, 12 Oct 2020 06:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508779; cv=none; d=google.com; s=arc-20160816; b=DTd1qjJmqu1X9EYx7MHco8LNREKgwuMYAgpeYTppEVnMjU6vOxAaVQIwfGmGly4vyN 56xVROeaXVVT2UZBqleEWrEZJC/EwGvXb+peeEWaWHpSUbdjESexkR+9C8LdqL/Lcj9W 7HC3BZ2kdFTQOUX8rjJYuaOA71TnrjuBHz3nTxQMWrs5SEivIgNm9pnF1t8KiT7x6xv3 19utQsqL4aRJLPMdoKlFiSZjPRIKDZeP8iJV4bqnIckGBrGBcUwy9WaHHzw9ANhaR1Dt DbcZY2lj7ZsIFK5e9aPhNH/NUrgc+n5hW9vovrMlxdS0VjmkA6cMwyJY9g4Omsg4PnPs 4axQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=oPtGyXytBwDyY7GLfqUK5ag6P/tIl9rUM7WWmVsOnzc=; b=ZfLJmJPD8knfQtyR0lF62yzZILJ9ssJwKtxLwBmsIFNNLhYL13EHl3EIvRFxSxRX3z M7+CNIMSeDVth37amIhXH1rWDgiJcu+O4vHeL2Q07LxE0OVIszHLOZhigglFyXGsc73L dZUkqNfbkk4SykXbS9p/Pk8pvSewYC3pSF3oRpNcmpzPWOKUAFaPuZHGMbarZn5cLmvM s6MIh35j3MzrZgLfC1lkzHq9cMic150U5k3KPRwRwCW7RJwTobjjID9MFUl0ObzG7Wja CFS9+fua7EMUMPhuMOXQqHJdLuqCOaJAyGJer4sy9YFvp2WwODs8s/jOxi3vX97RPDjl uNVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a2si11836700edr.352.2020.10.12.06.19.39; Mon, 12 Oct 2020 06:19:39 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388906AbgJLNTi (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:38 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:56920 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388890AbgJLNTi (ORCPT ); Mon, 12 Oct 2020 09:19:38 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A97ABE762066B92B16EE; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:26 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 06/11] arm64: dts: hisilicon: normalize the node name of the SMMU devices Date: Mon, 12 Oct 2020 21:17:34 +0800 Message-ID: <20201012131739.1655-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*". Otherwise, the errors similar to the following will be reported by arm,smmu-v3.yaml. smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*' Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 941d527dcb8668c..2f1930d4457fe1b 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -330,7 +330,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 36a873d150897b8..ba90b25853555b7 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1161,7 +1161,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; @@ -1170,7 +1170,7 @@ hisilicon,broken-prefetch-cmd; status = "disabled"; }; - p0_smmu_alg_a: smmu_alg@d0040000 { + p0_smmu_alg_a: iommu@d0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_a>; @@ -1183,7 +1183,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: iommu@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1196,7 +1196,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: iommu@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1209,7 +1209,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: iommu@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>;