| Message ID | 20201117201555.26723-4-dmurphy@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | [net-next,v4,1/4] ethtool: Add 10base-T1L link mode entries | expand |
On Tue, Nov 17, 2020 at 02:15:54PM -0600, Dan Murphy wrote: > The DP83TD510 is a 10M single twisted pair Ethernet PHY > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83td510.yaml | 64 +++++++++++++++++++ > 1 file changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml > > diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml > new file mode 100644 > index 000000000000..d3c97bb4d820 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml > @@ -0,0 +1,64 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 Texas Instruments Incorporated > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: TI DP83TD510 ethernet PHY > + > +allOf: > + - $ref: "ethernet-controller.yaml#" > + - $ref: "ethernet-phy.yaml#" > + > +maintainers: > + - Dan Murphy <dmurphy@ti.com> > + > +description: | > + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and > + RGMII interfaces. > + > + Specifications about the Ethernet PHY can be found at: > + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf > + > +properties: > + reg: > + maxItems: 1 > + > + tx-fifo-depth: > + description: | > + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble > + depths. The valid nibble depths are 4, 5, 6 and 8. > + enum: [ 4, 5, 6, 8 ] > + default: 5 > + > + rx-internal-delay-ps: > + description: | > + Setting this property to a non-zero number sets the RX internal delay > + for the PHY. The internal delay for the PHY is fixed to 30ns relative > + to receive data. I'm confused. The delay is 30ns +/- whatever is set here? > + > + tx-internal-delay-ps: > + description: | > + Setting this property to a non-zero number sets the TX internal delay > + for the PHY. The internal delay for the PHY has a range of -4 to 4ns > + relative to transmit data. Sounds like constraints? We do have a problem handling negative values though. Addressing in dtc was rejected, so we'll need to fixup the schema with unsigned values. But here it should just be negative values. > + > +unevaluatedProperties: false > + > +required: > + - reg > + > +examples: > + - | > + mdio0 { > + #address-cells = <1>; > + #size-cells = <0>; > + ethphy0: ethernet-phy@0 { > + reg = <0>; > + tx-rx-output-high; > + tx-fifo-depth = <5>; > + rx-internal-delay-ps = <1>; > + tx-internal-delay-ps = <1>; > + }; > + }; > -- > 2.29.2 >
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml new file mode 100644 index 000000000000..d3c97bb4d820 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI DP83TD510 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + - $ref: "ethernet-phy.yaml#" + +maintainers: + - Dan Murphy <dmurphy@ti.com> + +description: | + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and + RGMII interfaces. + + Specifications about the Ethernet PHY can be found at: + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf + +properties: + reg: + maxItems: 1 + + tx-fifo-depth: + description: | + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble + depths. The valid nibble depths are 4, 5, 6 and 8. + enum: [ 4, 5, 6, 8 ] + default: 5 + + rx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the RX internal delay + for the PHY. The internal delay for the PHY is fixed to 30ns relative + to receive data. + + tx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the TX internal delay + for the PHY. The internal delay for the PHY has a range of -4 to 4ns + relative to transmit data. + +unevaluatedProperties: false + +required: + - reg + +examples: + - | + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + tx-rx-output-high; + tx-fifo-depth = <5>; + rx-internal-delay-ps = <1>; + tx-internal-delay-ps = <1>; + }; + };
The DP83TD510 is a 10M single twisted pair Ethernet PHY Signed-off-by: Dan Murphy <dmurphy@ti.com> --- .../devicetree/bindings/net/ti,dp83td510.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml