diff mbox series

[6/6] arm64: dts: hisilicon: delete unused property smmu-cb-memtype

Message ID 20210118031634.934-7-thunder.leizhen@huawei.com
State Accepted
Commit ccf43e02012ae5c2fc895136ab0adf98286db40f
Headers show
Series further clean up Hisilicon-related errors detected by DT schema on arm64 | expand

Commit Message

Leizhen (ThunderTown) Jan. 18, 2021, 3:16 a.m. UTC 
The "smmu-cb-memtype" is a private property developed by the Hisilicon
driver in the early stage and is not used now. So delete it.

Otherwise, below YAML check warnings are reported:
arch/arm64/boot/dts/hisilicon/hip06-d03.dt.yaml: iommu@a0040000: \
'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/hisilicon/hip07-d05.dt.yaml: iommu@a0040000: \
'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>

---
 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 -
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 5 -----
 2 files changed, 6 deletions(-)

-- 
1.8.3
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 78050d67a78645b..7deca5f763d5037 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -335,7 +335,6 @@ 
 		reg = <0x0 0xa0040000 0x0 0x20000>;
 		#iommu-cells = <1>;
 		dma-coherent;
-		smmu-cb-memtype = <0x0 0x1>;
 		hisilicon,broken-prefetch-cmd;
 		status = "disabled";
 	};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index f477f442c275561..2172d807118143c 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1166,7 +1166,6 @@ 
 		reg = <0x0 0xa0040000 0x0 0x20000>;
 		#iommu-cells = <1>;
 		dma-coherent;
-		smmu-cb-memtype = <0x0 0x1>;
 		hisilicon,broken-prefetch-cmd;
 		status = "disabled";
 	};
@@ -1181,7 +1180,6 @@ 
 		#iommu-cells = <1>;
 		dma-coherent;
 		hisilicon,broken-prefetch-cmd;
-		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
 	p0_smmu_alg_b: iommu@8d0040000 {
 		compatible = "arm,smmu-v3";
@@ -1194,7 +1192,6 @@ 
 		#iommu-cells = <1>;
 		dma-coherent;
 		hisilicon,broken-prefetch-cmd;
-		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
 	p1_smmu_alg_a: iommu@400d0040000 {
 		compatible = "arm,smmu-v3";
@@ -1207,7 +1204,6 @@ 
 		#iommu-cells = <1>;
 		dma-coherent;
 		hisilicon,broken-prefetch-cmd;
-		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
 	p1_smmu_alg_b: iommu@408d0040000 {
 		compatible = "arm,smmu-v3";
@@ -1220,7 +1216,6 @@ 
 		#iommu-cells = <1>;
 		dma-coherent;
 		hisilicon,broken-prefetch-cmd;
-		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
 
 	soc {