From patchwork Wed Jan 27 07:08:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371482 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp4936jam; Tue, 26 Jan 2021 23:13:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJxPYrwefAtkEPqdv+EUBUQQJFNkwWJ//iM8+EE1tKld89wvW7dNYUxqr3yG4YtdOOHDepwt X-Received: by 2002:a17:907:932:: with SMTP id au18mr5674222ejc.91.1611731611558; Tue, 26 Jan 2021 23:13:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611731611; cv=none; d=google.com; s=arc-20160816; b=zIuxEnvQ5E+D3tVv5mUwzwJrzlz0ysWS8zMl/12gdVJwZ4fSbI3VrcDIETx8xJ3FMC QvcfIBr0di2J13mj160BMDI8m4v4jilnpPLEOuUfm+IFdqKP3jg4G1Hnd557ZT6CTMuo CyjQ9rPneryZSdmoBGpJBl+YNjcxbmCKPZCL0qbk6FXfzIy0N41mResH2UCuvp3wbMi9 J3LmUx+UutHB4D/dYc29xWQ+PT60d9uKzJta4w643b5bxS8+i2mh1mUWu3peJd4xpbrD VE2aoErQWGZ/BVkxhvEiHTIAeSBuGccXBu0aVf5mVtM1oBSEFXu9KxTS04V/tvPcJ280 wH/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JzPEw09FDG6IUtILV90vgM+UaMwcojiV04DDER7MbjE=; b=VCPBQu8Qe+yQdsVuXcwha1jkJMzQhLnFrimisp/oJJK/ctVj7Y0vfju2Q7PmSmZ7kL SF2NFY+awCIYWSYlihz6skSrrBbIeb2M98PAXsDFclHzQC1cTe5SR4BCi+NitsN2kKL2 6rwJf3psAmSOy0NM6c/Vmlam+9McraoLvB9dZUfDRWxdc3UYdlzDiWb11o7ZtxumI7JT +YDFEmS1TL2FjDLStz5D/smXiX8scfCmgd4YoIlfkbK/g8x46tj2Uxvvq4CqwTsSqBCC CzTb15ua5rxG5sTiLEvz3me4PCCJ5/8ulVmvSAatwbNDQe0KhLdbNz94xvBQ9UMWYW8R u8ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=NyumfzEE; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ga16si463787ejc.412.2021.01.26.23.13.31; Tue, 26 Jan 2021 23:13:31 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=NyumfzEE; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233178AbhA0HMs (ORCPT + 6 others); Wed, 27 Jan 2021 02:12:48 -0500 Received: from mail.kernel.org ([198.145.29.99]:45514 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232724AbhA0HJG (ORCPT ); Wed, 27 Jan 2021 02:09:06 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 51BF320731; Wed, 27 Jan 2021 07:08:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611731305; bh=qAqOPaONho9bc4dKl6lVor9L4nS0gWxyc03jsWmOUss=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NyumfzEEhM6ONoGXD2CMSV0LoAYyZ0FDwZmplvWue5WwS9kHnsOBi+5UgFRwii1BO v2Rgv5GXXlpqs/95Ndk5YMxGSH41PTVtuuqk4dcex1D6PpYWezVevxkHJvgfRXT/GT aHDsw9UWRAiTyhxemg3gQu/ohPz9drl9vG7Lu/81KSqRApULUhg9hFqaQh7+xqvtNt 2z+g9jaPSSlCxO2QNw/qP9TZatb3QqgTvRBqfWAAHeEAzu7kSesbI2Mn9gPZMwbAhN wp6GY6Z4IZU4J9n5YcLu3H6oFwU3WWS0eFGrrpnTLoJqeSH7yoDbWjE22K9md5oiap cVThXlGtuRDtA== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/5] clk: qcom: clk-alpha-pll: replace regval with val Date: Wed, 27 Jan 2021 12:38:07 +0530 Message-Id: <20210127070811.152690-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127070811.152690-1-vkoul@kernel.org> References: <20210127070811.152690-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Driver uses regval variable for holding register values, replace with a shorter one val Suggested-by: Stephen Boyd Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-alpha-pll.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.26.2 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 21c357c26ec4..f7721088494c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -777,15 +777,15 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, static int trion_pll_is_enabled(struct clk_alpha_pll *pll, struct regmap *regmap) { - u32 mode_regval, opmode_regval; + u32 mode_val, opmode_val; int ret; - ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval); - ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval); + ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); + ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); if (ret) return 0; - return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL)); + return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); } static int clk_trion_pll_is_enabled(struct clk_hw *hw) @@ -1445,12 +1445,12 @@ EXPORT_SYMBOL_GPL(clk_trion_pll_configure); static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 regval; + u32 val; int ret; /* Return early if calibration is not needed. */ - regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val); - if (regval & pcal_done) + regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); + if (val & pcal_done) return 0; /* On/off to calibrate */ @@ -1476,7 +1476,7 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; - u32 regval, l, alpha_width = pll_alpha_width(pll); + u32 val, l, alpha_width = pll_alpha_width(pll); u64 a; int ret; @@ -1497,8 +1497,8 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); - regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); - if (!(regval & ALPHA_PLL_ACK_LATCH)) { + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (!(val & ALPHA_PLL_ACK_LATCH)) { pr_err("Lucid PLL latch failed. Output may be unstable!\n"); return -EINVAL; }