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[109.252.193.52]) by smtp.gmail.com with ESMTPSA id a3sm2387993lfr.55.2021.03.14.09.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 09:48:18 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Paul Fertser , Rob Herring , Matt Merhar , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default Date: Sun, 14 Mar 2021 19:48:06 +0300 Message-Id: <20210314164810.26317-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210314164810.26317-1-digetx@gmail.com> References: <20210314164810.26317-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new Kconfig SOC_TEGRA_COMMON option which selects configuration options that are common for all Tegra SoCs. Select PM_OPP by default since from now on OPPs will be used by Tegra drivers which present on all SoC generations, like display controller driver for example. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 976dee036470..bcd61ae59ba3 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA20_VOLTAGE_COUPLER @@ -27,6 +28,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA30_VOLTAGE_COUPLER @@ -40,6 +42,7 @@ config ARCH_TEGRA_114_SOC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -51,6 +54,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -66,6 +70,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help @@ -77,6 +82,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -99,6 +105,7 @@ config ARCH_TEGRA_186_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a @@ -115,6 +122,7 @@ config ARCH_TEGRA_194_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra194 SoC. @@ -125,6 +133,7 @@ config ARCH_TEGRA_234_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra234 SoC. @@ -132,6 +141,10 @@ config ARCH_TEGRA_234_SOC endif endif +config SOC_TEGRA_COMMON + bool + select PM_OPP + config SOC_TEGRA_FUSE def_bool y depends on ARCH_TEGRA