| Message ID | 20210530171802.23649-2-paul@crapouillou.net |
|---|---|
| State | Accepted |
| Commit | 1660710cf5d8d44ec351a5df57c35516f1fbf5e0 |
| Headers | show |
| Series | Misc Ingenic patches | expand |
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ed51970c08e7..310ce50ad285 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -112,6 +112,7 @@ config MACH_INGENIC select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT select DMA_NONCOHERENT + select ARCH_HAS_SYNC_DMA_FOR_CPU select IRQ_MIPS_CPU select PINCTRL select GPIOLIB diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 212f3ce75a6b..3c4fc97b9f39 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void) case CPU_R12000: case CPU_BMIPS5000: case CPU_LOONGSON2EF: + case CPU_XBURST: return true; default: /*
I am not sure why this is required, but if this is not enabled, reading from a buffer in which data has been DMA'd may read incorrect values. This used to happen for instance in mmc_app_send_scr() (drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied by the CPU to a different location. Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- arch/mips/Kconfig | 1 + arch/mips/mm/dma-noncoherent.c | 1 + 2 files changed, 2 insertions(+)