| Message ID | 20220120232028.6738-4-ansuelsmth@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,01/15] dt-bindings: clock: permit additionalProprieties to qcom,gcc | expand |
On Fri, Jan 21, 2022 at 12:20:16AM +0100, Ansuel Smith wrote: > Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source > clocks. The gcc node is also used by the tsens driver, already documented, > to get the calib nvmem cells and the base reg from gcc. > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > --- > .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml > new file mode 100644 > index 000000000000..abc76a46b2ca > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +maintainers: > + - Ansuel Smith <ansuelsmth@gmail.com> > + > +description: | > + Qualcomm global clock control module which supports the clocks, resets and > + power domains on IPQ8064. > + > + See also: > + - dt-bindings/clock/qcom,gcc-ipq806x.h > + - dt-bindings/reset/qcom,gcc-ipq806x.h > + > +properties: This schema will never be applied because there is not a compatible property to use for matching. The base/common schema is the one that shouldn't have a compatible and then the specific schemas like this one do. > + clocks: > + items: > + - description: PXO source > + - description: CXO source > + > + clock-names: > + items: > + - const: pxo > + - const: cxo > + > + thermal-sensor: > + type: object > + > + allOf: > + - $ref: /schemas/thermal/qcom-tsens.yaml# > + > +required: > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + gcc: clock-controller@900000 { > + compatible = "qcom,gcc-ipq8064", "syscon"; > + reg = <0x00900000 0x4000>; > + clocks = <&pxo_board>, <&cxo_board>; > + clock-names = "pxo", "cxo"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + tsens: thermal-sensor { > + compatible = "qcom,ipq8064-tsens"; > + > + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; > + nvmem-cell-names = "calib", "calib_backup"; > + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow"; > + > + #qcom,sensors = <11>; > + #thermal-sensor-cells = <1>; > + }; > + }; > -- > 2.33.1 > >
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file mode 100644 index 000000000000..abc76a46b2ca --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc.yaml# + +maintainers: + - Ansuel Smith <ansuelsmth@gmail.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.h + - dt-bindings/reset/qcom,gcc-ipq806x.h + +properties: + clocks: + items: + - description: PXO source + - description: CXO source + + clock-names: + items: + - const: pxo + - const: cxo + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + };
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> --- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml