Message ID | 20220218002956.6590-7-ansuelsmth@gmail.com |
---|---|
State | New |
Headers | show |
Series | [v2,01/18] ARM: dts: qcom: add multiple missing pin definition for ipq8064 | expand |
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 9d658fcc1f12..e247bf51df01 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1175,8 +1175,6 @@ hs_phy_0: phy@100f8800 { clocks = <&gcc USB30_0_UTMI_CLK>; clock-names = "ref"; #phy-cells = <0>; - - status = "disabled"; }; ss_phy_0: phy@100f8830 { @@ -1185,8 +1183,6 @@ ss_phy_0: phy@100f8830 { clocks = <&gcc USB30_0_MASTER_CLK>; clock-names = "ref"; #phy-cells = <0>; - - status = "disabled"; }; usb3_0: usb3@100f8800 {
Enable usb phy by default. When the usb phy were pushed, half of them were flagged as disabled by mistake. Fix this to correctly init dwc3 node on any ipq8064 based SoC. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ---- 1 file changed, 4 deletions(-)