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[79.47.249.147]) by smtp.googlemail.com with ESMTPSA id w6-20020a5d6806000000b002036515dda7sm2396699wru.33.2022.03.09.11.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 11:15:32 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ansuel Smith , Jonathan McDowell Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for ipq8064 Date: Wed, 9 Mar 2022 20:01:47 +0100 Message-Id: <20220309190152.7998-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220309190152.7998-1-ansuelsmth@gmail.com> References: <20220309190152.7998-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add opp table for cpu and l2 cache. While the current cpufreq is the generic one that doesn't scale the L2 cache, we add the l2 cache opp anyway for the sake of completeness. This will be handy in the future when a dedicated cpufreq driver is introduced for krait cores that will correctly scale l2 cache with the core freq. Opp-level is set based on the logic of 0: idle level 1: normal level 2: turbo level Signed-off-by: Ansuel Smith Tested-by: Jonathan McDowell --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 7dd0b901cd30..a1079583def9 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -48,6 +48,105 @@ L2: l2-cache { }; }; + opp_table_l2: opp_table_l2 { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <100000>; + opp-level = <0>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <100000>; + opp-level = <1>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; + }; + + opp_table0: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <0>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <1>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <1>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <1>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; + opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; + }; + thermal-zones { sensor0-thermal { polling-delay-passive = <0>;