From patchwork Fri Mar 11 08:33:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 550639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CEF8C433EF for ; Fri, 11 Mar 2022 08:33:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233043AbiCKIep (ORCPT ); Fri, 11 Mar 2022 03:34:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233540AbiCKIen (ORCPT ); Fri, 11 Mar 2022 03:34:43 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58F8718C78E for ; Fri, 11 Mar 2022 00:33:40 -0800 (PST) Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nSaiL-0000aN-6g; Fri, 11 Mar 2022 09:33:33 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nSaiE-0040gk-Hb; Fri, 11 Mar 2022 09:33:26 +0100 From: Sascha Hauer To: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, Andy Yan , Benjamin Gaignard , Michael Riesch , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Peter Geis , Sascha Hauer Subject: [PATCH v8 09/24] drm/rockchip: dw_hdmi: Add support for niu clk Date: Fri, 11 Mar 2022 09:33:08 +0100 Message-Id: <20220311083323.887372-10-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220311083323.887372-1-s.hauer@pengutronix.de> References: <20220311083323.887372-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rk3568 HDMI has an additional clock that needs to be enabled for the HDMI controller to work. This clock is not needed for the HDMI controller itself, but to make the SoC internal bus logic work. From the reference manual: > 2.8.6 NIU Clock gating reliance > > A part of niu clocks have a dependence on another niu clock in order to > sharing the internal bus. When these clocks are in use, another niu > clock must be opened, and cannot be gated. These clocks and the special > clock on which they are relied are as following: > > Clocks which have dependency The clock which can not be gated > ----------------------------------------------------------------- > ... > pclk_vo_niu, hclk_vo_s_niu hclk_vo_niu > ... The clock framework does not support turning on a clock whenever another clock is turned on, so this patch adds support for the dependent clock to the HDMI driver. We call it "NIU", which is for "Native Interface Unit" Signed-off-by: Sascha Hauer --- Notes: Changes since v7: - rename hclk to niu drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index fe4f9556239ac..7adf9044cb73b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -76,6 +76,7 @@ struct rockchip_hdmi { const struct rockchip_hdmi_chip_data *chip_data; struct clk *ref_clk; struct clk *grf_clk; + struct clk *niu_clk; struct dw_hdmi *hdmi; struct regulator *avdd_0v9; struct regulator *avdd_1v8; @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) return PTR_ERR(hdmi->grf_clk); } + hdmi->niu_clk = devm_clk_get_optional(hdmi->dev, "niu"); + if (PTR_ERR(hdmi->niu_clk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(hdmi->niu_clk)) { + DRM_DEV_ERROR(hdmi->dev, "failed to get niu clock\n"); + return PTR_ERR(hdmi->niu_clk); + } + hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); if (IS_ERR(hdmi->avdd_0v9)) return PTR_ERR(hdmi->avdd_0v9); @@ -596,6 +605,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, goto err_clk; } + ret = clk_prepare_enable(hdmi->niu_clk); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI hclk clock: %d\n", + ret); + goto err_clk; + } + if (hdmi->chip_data == &rk3568_chip_data) { regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |