From patchwork Fri May 13 13:16:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18DAAC4321E for ; Fri, 13 May 2022 13:17:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380629AbiEMNRE (ORCPT ); Fri, 13 May 2022 09:17:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380611AbiEMNRA (ORCPT ); Fri, 13 May 2022 09:17:00 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BA9C9FE2 for ; Fri, 13 May 2022 06:16:59 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id bq30so14503709lfb.3 for ; Fri, 13 May 2022 06:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lFsusYv3a39AFVrKGs8AUQpmcs9BSd1N8sKJb+8VaT8=; b=A3179lU63szutmxhPvGslI9RJC7xFW3O4znMiwFdE9HbGhkQPHYLAURU0aVUwAOB45 aZj5V872Ou5U9hHXnvxVyH73OxpCg1UJ8KX2RZiKbInwbU5VI5D8vP3HXX/s8a9KyaGT nz41YomRf7VwH6k9aKym80nM8Jlxmy21E3sIldeSkttS4+ivNNtzVjqfTp+ytcHYuM9U D3CY2erlpaCPiKYVtEa/3ZDWMQQ7WNdcop9XrXLse7ZLrqWe0zHuas7qBEsXGjYzeUE/ H/mp4fGjCugJsGduHn0yRZYt8BoQHjyHDv0HTWv95/vHMoXqtc+Tf7iZ44g3WCkx09W/ NkSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lFsusYv3a39AFVrKGs8AUQpmcs9BSd1N8sKJb+8VaT8=; b=PC8DoJ1EUAPCB5XfsMBlpnCTrDJYYKpZJ2FmPSNjtq+2M2j4vv3j1gZqNmhTSQjnqu OzUM5/e3NauknRo3FFzsAQwadphji0gV91DDffODQX3iBbwrxpys0q2XAbANUhBX3Ntj oFsFGCw2C20Iz3oiqr+n84gRNszbjuuJjApodMzsBOxy4/pXGJVlqLpdNfqNN9qhWehP pJlLIBkGKgbOuO+GFTgc0JCiAhcTFVaJA1y1qZh57VzmfMzdMBWUTQ1cWy+Fs11uGY4C wSfXTGia3PgJxgfg/uu/G/EADTwWL6k+f8ucyYEiJ8jOV5xHgVrbH7PP9yGh1ElpbUmv QCTw== X-Gm-Message-State: AOAM530Ht9QIo/pz5l6rzxWWrDTBdVoKO3/esKiw6TpYXygXt8YcQIHa j5b0mLLrYhPsrlScmjrc/7TPeg== X-Google-Smtp-Source: ABdhPJyTmh7MD56QpxDuLJCZb27DBkeV4oCCjErOb9iEsu8weZ73LCEv6keKQQjgw8rx54H0jsYOxQ== X-Received: by 2002:a05:6512:2215:b0:473:c124:434b with SMTP id h21-20020a056512221500b00473c124434bmr3498161lfu.24.1652447817796; Fri, 13 May 2022 06:16:57 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u22-20020a2ea176000000b0024f3d1dae8fsm436991ljl.23.2022.05.13.06.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 06:16:56 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Johan Hovold Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v9 01/10] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Date: Fri, 13 May 2022 16:16:46 +0300 Message-Id: <20220513131655.2927616-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513131655.2927616-1-dmitry.baryshkov@linaro.org> References: <20220513131655.2927616-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org I have replied with my Tested-by to the patch at [2], which has landed in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints"). However lately I noticed that during the tests I still had 'pcie_pme=nomsi', so the device was not forced to use higher MSI vectors. After removing this option I noticed that high MSI vectors are not delivered on tested platforms. Additional research pointed to a patch in msm-4.14 ([1]), which describes that each group of MSI vectors is mapped to the separate interrupt. Without these changes specifying num_vectors can lead to missing MSI interrupts and thus to devices malfunction. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/671a3d5f129f4bfe477152292ada2194c8440d22 [2] https://lore.kernel.org/linux-arm-msm/20211214101319.25258-1-manivannan.sadhasivam@linaro.org/ Fixes: 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints") Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f9a61ad6d1f0..2e5464edc36e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1587,7 +1587,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; pp = &pci->pp; - pp->num_vectors = MAX_MSI_IRQS; pcie->pci = pci;