From patchwork Sun May 7 18:23:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 679804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41073C77B75 for ; Sun, 7 May 2023 18:34:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbjEGSeW (ORCPT ); Sun, 7 May 2023 14:34:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231472AbjEGSeU (ORCPT ); Sun, 7 May 2023 14:34:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 096EA9EE8; Sun, 7 May 2023 11:34:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8FAF86119E; Sun, 7 May 2023 18:34:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F993C433D2; Sun, 7 May 2023 18:34:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484459; bh=Cwi9G0RC9sDhCBbFheRaOVgx+rmiAvtJuPLG5ht1r7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uNMPk3ntZAVS8YwlGv7g0/1DxLS+CXoeUiidi4/241Adf5EX2uPx2Ky9DwASPEh9P tlnzGdYjzsgWdMnSbcVsFbQBkNwMNDiI4ceLzELguWR78J0trAbI/463xvg2mGEKSz bUdNrvv8fgJ7YTZYWyWPg5bPNCyr7rMZyvkSM4VEzTtEX2/1HjNb7bq8J4HL9Hl83z SEaXt+7YLPVlPuSIBZ6vLJEZFk75f2J/oqpDKppyCOxKVxYoOd9z/H5zbisZ0NmT2P 5XW600//wLg/3j+ctQVwLf0s7QvgsztjxL+oa3vs58PktKJBcGCOY6YdVjk/GD7Hl8 pdupIoJGBLpbQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Date: Mon, 8 May 2023 02:23:01 +0800 Message-Id: <20230507182304.2934-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The first SoC in the T-HEAD series is light(a.k.a th1520), containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT