From patchwork Sat Jun 17 16:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 693716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7B8BEB64DB for ; Sat, 17 Jun 2023 16:27:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345949AbjFQQ1O (ORCPT ); Sat, 17 Jun 2023 12:27:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345967AbjFQQ1L (ORCPT ); Sat, 17 Jun 2023 12:27:11 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6222D173B; Sat, 17 Jun 2023 09:27:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E9A5D60F71; Sat, 17 Jun 2023 16:27:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1AE5C433CD; Sat, 17 Jun 2023 16:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019228; bh=9TcP0pheewMFNteE2MjQt4eyImwOKciOqR8+Aqc04aI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BPnAUsh93U3aeHBUKqzv4wIHLB3IOdV2/E6/coVGuZyPoQ34uckzFBlxTg2W2TApd ElOmw92e7gpvrpqZCj0LR+ePdZPnWiSteQwpULo5lNfTQOo09E1ViF2YbdCqlblh/w rzqy68lX5qbuPf2pI6lR8Y7gEFVwSOAqtFHoZ3wGgQ6jaHe+WzG98kZ4LEQE6z0fKW pnWBbX5XYpiKkX1QOk5psdB1DfcRGUF/Upf+63t+59b5/xuyi7BoIfzBeMFFpNvY2/ weom9JS1O9tQqeAkZv0pDRso9V9TXdymiQr0zAHnAzWjSoMzWxbbgCoVnYl+E2ywLP EphWZrBIzsKew== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Date: Sun, 18 Jun 2023 00:15:25 +0800 Message-Id: <20230617161529.2092-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT