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[83.9.29.26]) by smtp.gmail.com with ESMTPSA id s9-20020a2e9c09000000b002b6995f38a2sm4946224lji.100.2023.07.03.11.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 11:20:20 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Jul 2023 20:20:12 +0200 Subject: [PATCH v2 8/8] arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC MIME-Version: 1.0 Message-Id: <20230622-topic-8998clk-v2-8-6222fbc2916b@linaro.org> References: <20230622-topic-8998clk-v2-0-6222fbc2916b@linaro.org> In-Reply-To: <20230622-topic-8998clk-v2-0-6222fbc2916b@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeffrey Hugo , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1688408407; l=1108; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=rcLA8twyqUlcJD4D43vneN0vw2noKKbjZxFdyfHDJZM=; b=J9qF1k7V2CcK1QdJjF8lyl9xKqY04T25afPjuYYxmly9bH9mpvemJtiRXtaKrrEaWRVNontZE 8X79xc6aeF3D7pgVQuJGJEZIkWOOAAtyaan6pgi66L4r5buBBT1lL5i X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. We've already been using the correct one in the non-div case, start doing so for the other one as well. Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 74bd05579796..c4faba092368 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2718,7 +2718,8 @@ mmcc: clock-controller@c8c0000 { "dsi1byte", "hdmipll", "dplink", - "dpvco"; + "dpvco", + "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, <0>, @@ -2727,7 +2728,8 @@ mmcc: clock-controller@c8c0000 { <0>, <0>, <0>, - <0>; + <0>, + <&gcc GCC_MMSS_GPLL0_DIV_CLK>; }; mmss_smmu: iommu@cd00000 {