From patchwork Thu Jul 13 12:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 702394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3092C0015E for ; Thu, 13 Jul 2023 12:12:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234556AbjGMMMn (ORCPT ); Thu, 13 Jul 2023 08:12:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234540AbjGMMMj (ORCPT ); Thu, 13 Jul 2023 08:12:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1AF2212B; Thu, 13 Jul 2023 05:12:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250358; x=1720786358; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZKaRuGdjiNCn7C7n8xPfX596TIEq0qNYdoQyUSZd1aQ=; b=04jp033/brd3VT4ZhZGJQ4bS08OMG0cHUdOt+xASyRFX663GWiwMI4hb nDm2IS4aQJi6TFdIojp0novaPB0c0FHUl3XA9gonw7Yp5qo6M9WWgIpa6 AGW4BZnid2SyqbKjXEVrR6ClTgE9RFO9fcF+0Q/WQaHeCHvw0+hCe0d6Q yBbUjETZV2xuUBV/2CUfmdKmD3vA5UI6x+BdO6833o85rTy7mZ64GRk+i EfcvvqqsxoRqYWirq3T8Lnnx+AJE+Uu0e6oiaP6vlzk0DCWOkVbtuf4Jg tTGvaqDP2kx4oJrzHWsdtoobeAsB+ttqEcpyyX/HmS3Agi7Impnc1tymo g==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="222827129" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:37 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:35 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:33 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Date: Thu, 13 Jul 2023 13:11:00 +0100 Message-ID: <20230713-masculine-saddlebag-67a94966b091@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2526; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=n3RvV1kp7c1RvguDNV0TNjeqOvB9izEszUM2SQOrTeY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX149JbjSUWVN7fvXGoYZWev/2c4TbS8NXnJQivdtRfnx E/GmHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIiQ6Gf5orprUbu2163Z6h77bFXm j5ybfWV/a3vbPWlxT7tcfbeTsjwzF77nCRZUKTWvUdzrOm8Xht1Dp4/Hlo6JGAWetC3T5a8gIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Heiko Stuebner When filling hwcap the kernel already expects the isa string to start with rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT. So when recreating the runtime isa-string we can also just go the other way to get the correct starting point for it. Signed-off-by: Heiko Stuebner Reviewed-by: Andrew Jones Reviewed-by: Evan Green Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley --- Changes in v3: - Fix tabbing of print_mmu() Changes in v2: - Delete the whole else & pull print_mmu() above it, since that's common code now --- arch/riscv/kernel/cpu.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3af2d214ce21..f808b67f5a27 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -257,13 +257,16 @@ static void print_isa_ext(struct seq_file *f) */ static const char base_riscv_exts[13] = "imafdqcbkjpvh"; -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { int i; seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); + if (IS_ENABLED(CONFIG_32BIT)) + seq_write(f, "rv32", 4); + else + seq_write(f, "rv64", 4); + for (i = 0; i < sizeof(base_riscv_exts); i++) { if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) /* Print only enabled the base ISA extensions */ @@ -320,27 +323,21 @@ static int c_show(struct seq_file *m, void *v) unsigned long cpu_id = (unsigned long)v - 1; struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); struct device_node *node; - const char *compat, *isa; + const char *compat; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); + print_isa(m); + print_mmu(m); if (acpi_disabled) { node = of_get_cpu_node(cpu_id, NULL); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) seq_printf(m, "uarch\t\t: %s\n", compat); of_node_put(node); - } else { - if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) - print_isa(m, isa); - - print_mmu(m); } seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);