From patchwork Wed Aug 2 20:53:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 709347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACB8DC04FDF for ; Wed, 2 Aug 2023 20:53:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232665AbjHBUx1 (ORCPT ); Wed, 2 Aug 2023 16:53:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229801AbjHBUxY (ORCPT ); Wed, 2 Aug 2023 16:53:24 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D473C26B5; Wed, 2 Aug 2023 13:53:22 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrH1G109460; Wed, 2 Aug 2023 15:53:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009597; bh=t0NFPm/eBGsI8PsBULav5hRKKRo235LNB1aMsQWzZIc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N+WpwMIxhKB8CkjOZxM6bMRs6mi5EvcCgW2R6RAhqjBpEapMVGyIxxPDnElyio5Va pMBNtgYR9RkqSF1ehxFpLa9rJYNHhHkniiJ0hBdSXxRfFcEE1euaM49ko7juF8cslt lq0SmNFS4sey9bhbJEqPLFuS5wdMHN49w8aljtYQ= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrHxJ018948 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:17 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:17 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:16 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASH090834; Wed, 2 Aug 2023 15:53:16 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , CC: , , Andrew Davis Subject: [PATCH 10/13] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level Date: Wed, 2 Aug 2023 15:53:06 -0500 Message-ID: <20230802205309.257392-11-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++-------------- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 3 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index dee9056f56051..4a5c4f36baeec 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -240,27 +240,17 @@ &main_uart3 { pinctrl-0 = <&main_uart3_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; +&main_gpio0 { + status = "okay"; + /* default pins */ }; &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; -&wkup_gpio1 { - status = "disabled"; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5d7542ba41b93..6a776f3bbcb19 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 571eb0e2eac92..5ae7320efad7b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_navss: bus@28380000 {