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From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <conor@kernel.org>, <robh+dt@kernel.org>,
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 Chien Peter Lin" <peterlin@andestech.com>
Subject: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to
 interrupt-controller
Date: Thu, 19 Oct 2023 21:59:05 +0800
Message-ID: <20231019135905.3658215-1-peterlin@andestech.com>
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Add "andestech,cpu-intc" compatible string for Andes INTC which
provides Andes-specific IRQ chip functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..5b216e11c69f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -99,7 +99,9 @@ properties:
         const: 1
 
       compatible:
-        const: riscv,cpu-intc
+        enum:
+          - riscv,cpu-intc
+          - andestech,cpu-intc
 
       interrupt-controller: true