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Some platform (such as Layerscape) require correct setting for dma-coherent. But default value is wrong in chips. Signed-off-by: Frank Li --- drivers/usb/dwc3/core.c | 33 +++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 37 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 3b68e8e45b8b9..c72929b122014 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -948,6 +948,37 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) static int dwc3_core_get_phy(struct dwc3 *dwc); static int dwc3_core_ulpi_init(struct dwc3 *dwc); +static void dwc3_set_bus_req_info(struct dwc3 *dwc) +{ + struct device *dev = dwc->dev; + u32 cfg; + u8 val; + + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + + if (!device_property_read_u8(dev, "snps,des-wr-reqinfo", &val)) { + cfg &= ~DWC3_GSBUSCFG0_DESWRREQINFO_MASK; + cfg |= FIELD_PREP(DWC3_GSBUSCFG0_DESWRREQINFO_MASK, val); + } + + if (!device_property_read_u8(dev, "snps,des-rd-reqinfo", &val)) { + cfg &= ~DWC3_GSBUSCFG0_DESRDREQINFO_MASK; + cfg |= FIELD_PREP(DWC3_GSBUSCFG0_DESRDREQINFO_MASK, val); + } + + if (!device_property_read_u8(dev, "snps,dat-wr-reqinfo", &val)) { + cfg &= ~DWC3_GSBUSCFG0_DATWRREQINFO_MASK; + cfg |= FIELD_PREP(DWC3_GSBUSCFG0_DATWRREQINFO_MASK, val); + } + + if (!device_property_read_u8(dev, "snps,dat-rd-reqinfo", &val)) { + cfg &= ~DWC3_GSBUSCFG0_DATRDREQINFO_MASK; + cfg |= FIELD_PREP(DWC3_GSBUSCFG0_DATRDREQINFO_MASK, val); + } + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); +} + /* set global incr burst type configuration registers */ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) { @@ -1256,6 +1287,8 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_set_incr_burst_type(dwc); + dwc3_set_bus_req_info(dwc); + ret = dwc3_phy_power_on(dwc); if (ret) goto err_exit_phy; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index df544ec730d22..cf64cfc0f208a 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -186,6 +186,10 @@ #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff +#define DWC3_GSBUSCFG0_DESWRREQINFO_MASK GENMASK(19, 16) +#define DWC3_GSBUSCFG0_DATWRREQINFO_MASK GENMASK(23, 20) +#define DWC3_GSBUSCFG0_DESRDREQINFO_MASK GENMASK(27, 24) +#define DWC3_GSBUSCFG0_DATRDREQINFO_MASK GENMASK(31, 28) /* Global Debug LSP MUX Select */ #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */