[v12,09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI

Message ID	20240127161753.114685-10-apatel@ventanamicro.com
State	New
Headers	show Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B72AD44C68 for <devicetree@vger.kernel.org>; Sat, 27 Jan 2024 16:19:10 +0000 (UTC) From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Frank Rowand <frowand.list@gmail.com>, Conor Dooley <conor+dt@kernel.org> Cc: Marc Zyngier <maz@kernel.org>, =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>, Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Saravana Kannan <saravanak@google.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v12 09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI Date: Sat, 27 Jan 2024 21:47:37 +0530 Message-Id: <20240127161753.114685-10-apatel@ventanamicro.com> In-Reply-To: <20240127161753.114685-1-apatel@ventanamicro.com> References: <20240127161753.114685-1-apatel@ventanamicro.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	[v12,01/25] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count \| expand [v12,01/25] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count [v12,03/25] genirq/msi: Extend msi_parent_ops [v12,05/25] platform-msi: Prepare for real per device domains [v12,07/25] genirq/msi: Provide optional translation op [v12,09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI [v12,11/25] genirq/msi: Provide allocation/free functions for "wired" MSI interrupts [v12,13/25] genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV [v12,15/25] irqchip/riscv-intc: Add support for RISC-V AIA [v12,17/25] genirq/matrix: Dynamic bitmap allocation [v12,19/25] irqchip/riscv-imsic: Add device MSI domain support for platform devices [v12,21/25] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC [v12,23/25] irqchip/riscv-aplic: Add support for MSI-mode [v12,24/25] RISC-V: Select APLIC and IMSIC drivers

Message ID

20240127161753.114685-10-apatel@ventanamicro.com

State

New

Headers

From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>,
 =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>,
 Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>,
 Sunil V L <sunilvl@ventanamicro.com>, Saravana Kannan <saravanak@google.com>,
 Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v12 09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI
Date: Sat, 27 Jan 2024 21:47:37 +0530
Message-Id: <20240127161753.114685-10-apatel@ventanamicro.com>
In-Reply-To: <20240127161753.114685-1-apatel@ventanamicro.com>
References: <20240127161753.114685-1-apatel@ventanamicro.com>
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MIME-Version: 1.0
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Series

[v12,01/25] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count | expand

Commit Message

Anup Patel Jan. 27, 2024, 4:17 p.m. UTC

From: Thomas Gleixner <tglx@linutronix.de>

Provide a domain bus token for the upcoming support for wire to MSI device
domains so the domain can be distinguished from regular device MSI domains.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 include/linux/irqdomain_defs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h
index 4c69151cb9d2..f59d2e9941a2 100644
--- a/include/linux/irqdomain_defs.h
+++ b/include/linux/irqdomain_defs.h
@@ -27,6 +27,7 @@  enum irq_domain_bus_token {
 	DOMAIN_BUS_AMDVI,
 	DOMAIN_BUS_PCI_DEVICE_IMS,
 	DOMAIN_BUS_DEVICE_IMS,
+	DOMAIN_BUS_WIRED_TO_MSI,
 };
 
 #endif /* _LINUX_IRQDOMAIN_DEFS_H */

[v12,09/25] genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI

Commit Message

Patch