From patchwork Wed Jan 6 07:37:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 357710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08627C4332D for ; Wed, 6 Jan 2021 07:38:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C75462310A for ; Wed, 6 Jan 2021 07:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726381AbhAFHie (ORCPT ); Wed, 6 Jan 2021 02:38:34 -0500 Received: from guitar.tcltek.co.il ([192.115.133.116]:36286 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726323AbhAFHie (ORCPT ); Wed, 6 Jan 2021 02:38:34 -0500 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id A3711440846; Wed, 6 Jan 2021 09:37:50 +0200 (IST) From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Lee Jones , Linus Walleij , Bartosz Golaszewski , Rob Herring Cc: Baruch Siach , Andrew Lunn , Gregory Clement , Russell King , Sebastian Hesselbarth , Thomas Petazzoni , Chris Packham , Sascha Hauer , Ralph Sennhauser , linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v6 3/4] arm64: dts: armada: add pwm offsets for ap/cp gpios Date: Wed, 6 Jan 2021 09:37:39 +0200 Message-Id: <25106a9672027ecdf7d668a04cd9ba616c2dbd7b.1609917364.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) point to the same counter registers offset. The driver will decide how to use counters A/B. This is different from the convention of pwm on earlier Armada series (370/38x). On those systems the assignment of A/B counters to GPIO blocks is coded in both DT and the driver. The actual behaviour of the current driver on Armada 8K/7K is the same as earlier systems. Add also clock properties for base pwm frequency reference. Signed-off-by: Baruch Siach --- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 +++ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 12e477f1aeb9..6614472100c2 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -281,6 +281,9 @@ ap_gpio: gpio@1040 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&ap_pinctrl 0 0 20>; + marvell,pwm-offset = <0x10c0>; + #pwm-cells = <2>; + clocks = <&ap_clk 3>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 994a2fce449a..d774a39334d9 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; + marvell,pwm-offset = <0x1f0>; + #pwm-cells = <2>; interrupt-controller; interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, <85 IRQ_TYPE_LEVEL_HIGH>, <84 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; + clock-names = "core", "axi"; + clocks = <&CP11X_LABEL(clk) 1 21>, + <&CP11X_LABEL(clk) 1 17>; status = "disabled"; }; @@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; + marvell,pwm-offset = <0x1f0>; + #pwm-cells = <2>; interrupt-controller; interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, <81 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <79 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; + clock-names = "core", "axi"; + clocks = <&CP11X_LABEL(clk) 1 21>, + <&CP11X_LABEL(clk) 1 17>; status = "disabled"; }; };