| Message ID | 41d67d36481f3099f953a462a80e99a4fcd477dd.1666549145.git.lorenzo@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,net-next,1/6] arm64: dts: mediatek: mt7986: add support for RX Wireless Ethernet Dispatch | expand |
> On 23/10/2022 14:28, Lorenzo Bianconi wrote: > > Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet > > Dispatch to offload traffic received by the wlan interface to lan/wan > > one. > > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel. Hi Krzysztof, Ack, sorry. I will do it in v3. > > > > > Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com> > > Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > > --- > > arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 73 +++++++++++++++++++++++ > > 1 file changed, 73 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > > index 72e0d9722e07..e3b05280dcb6 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > > @@ -8,6 +8,7 @@ > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/clock/mt7986-clk.h> > > #include <dt-bindings/reset/mt7986-resets.h> > > +#include <dt-bindings/reset/ti-syscon.h> > > > > / { > > interrupt-parent = <&gic>; > > @@ -76,6 +77,31 @@ wmcpu_emi: wmcpu-reserved@4fc00000 { > > no-map; > > reg = <0 0x4fc00000 0 0x00100000>; > > }; > > + > > + wo_emi0: wo-emi0@4fd00000 { > > + reg = <0 0x4fd00000 0 0x40000>; > > + no-map; > > + }; > > + > > + wo_emi1: wo-emi1@4fd40000 { > > + reg = <0 0x4fd40000 0 0x40000>; > > + no-map; > > + }; > > + > > + wo_ilm0: wo-ilm0@151e0000 { > > + reg = <0 0x151e0000 0 0x8000>; > > + no-map; > > + }; > > + > > + wo_ilm1: wo-ilm1@151f0000 { > > + reg = <0 0x151f0000 0 0x8000>; > > + no-map; > > + }; > > + > > + wo_data: wo-data@4fd80000 { > > + reg = <0 0x4fd80000 0 0x240000>; > > + no-map; > > + }; > > }; > > > > timer { > > @@ -226,6 +252,12 @@ ethsys: syscon@15000000 { > > reg = <0 0x15000000 0 0x1000>; > > #clock-cells = <1>; > > #reset-cells = <1>; > > + > > + ethsysrst: reset-controller { > > + compatible = "ti,syscon-reset"; > > + #reset-cells = <1>; > > + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; > > + }; > > }; > > > > wed_pcie: wed-pcie@10003000 { > > @@ -240,6 +272,10 @@ wed0: wed@15010000 { > > reg = <0 0x15010000 0 0x1000>; > > interrupt-parent = <&gic>; > > interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; > > + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>; > > + mediatek,wo-ccif = <&wo_ccif0>; > > + mediatek,wo-dlm = <&wo_dlm0>; > > + mediatek,wo-boot = <&wo_boot>; > > }; > > > > wed1: wed@15011000 { > > @@ -248,6 +284,43 @@ wed1: wed@15011000 { > > reg = <0 0x15011000 0 0x1000>; > > interrupt-parent = <&gic>; > > interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; > > + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>; > > + mediatek,wo-ccif = <&wo_ccif1>; > > + mediatek,wo-dlm = <&wo_dlm1>; > > + mediatek,wo-boot = <&wo_boot>; > > + }; > > + > > + wo_ccif0: wo-ccif1@151a5000 { > > Node names should be generic. > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > > "1" suffix is for sure not generic. Neither wo-ccif is... unless there > is some article on Wikipedia about it? Or maybe generic name is not > possible to get, which happens... I think we can use "syscon" for wo_ccif and wo_boot. I can't find a better name for wo_dlm since afaik it is a hw ring used for packet processing. What do you think? Regards, Lorenzo > > > + compatible = "mediatek,mt7986-wo-ccif","syscon"; > > + reg = <0 0x151a5000 0 0x1000>; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + wo_ccif1: wo-ccif1@151ad000 { > > + compatible = "mediatek,mt7986-wo-ccif","syscon"; > > + reg = <0 0x151ad000 0 0x1000>; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + wo_dlm0: wo-dlm@151e8000 { > > + compatible = "mediatek,mt7986-wo-dlm"; > > + reg = <0 0x151e8000 0 0x2000>; > > + resets = <ðsysrst 0>; > > + reset-names = "wocpu_rst"; > > + }; > > + > > + wo_dlm1: wo-dlm@0x151f8000 { > > + compatible = "mediatek,mt7986-wo-dlm"; > > + reg = <0 0x151f8000 0 0x2000>; > > + resets = <ðsysrst 0>; > > + reset-names = "wocpu_rst"; > > + }; > > + > > + wo_boot: wo-boot@15194000 { > > + compatible = "mediatek,mt7986-wo-boot","syscon"; > > Missing space. > > > + reg = <0 0x15194000 0 0x1000>; > > }; > > > > eth: ethernet@15100000 { > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 72e0d9722e07..e3b05280dcb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/reset/ti-syscon.h> / { interrupt-parent = <&gic>; @@ -76,6 +77,31 @@ wmcpu_emi: wmcpu-reserved@4fc00000 { no-map; reg = <0 0x4fc00000 0 0x00100000>; }; + + wo_emi0: wo-emi0@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_emi1: wo-emi1@4fd40000 { + reg = <0 0x4fd40000 0 0x40000>; + no-map; + }; + + wo_ilm0: wo-ilm0@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_ilm1: wo-ilm1@151f0000 { + reg = <0 0x151f0000 0 0x8000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; }; timer { @@ -226,6 +252,12 @@ ethsys: syscon@15000000 { reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; + }; }; wed_pcie: wed-pcie@10003000 { @@ -240,6 +272,10 @@ wed0: wed@15010000 { reg = <0 0x15010000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif0>; + mediatek,wo-dlm = <&wo_dlm0>; + mediatek,wo-boot = <&wo_boot>; }; wed1: wed@15011000 { @@ -248,6 +284,43 @@ wed1: wed@15011000 { reg = <0 0x15011000 0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_data>; + mediatek,wo-ccif = <&wo_ccif1>; + mediatek,wo-dlm = <&wo_dlm1>; + mediatek,wo-boot = <&wo_boot>; + }; + + wo_ccif0: wo-ccif1@151a5000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_ccif1: wo-ccif1@151ad000 { + compatible = "mediatek,mt7986-wo-ccif","syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_dlm0: wo-dlm@151e8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wo_dlm1: wo-dlm@0x151f8000 { + compatible = "mediatek,mt7986-wo-dlm"; + reg = <0 0x151f8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wo_boot: wo-boot@15194000 { + compatible = "mediatek,mt7986-wo-boot","syscon"; + reg = <0 0x15194000 0 0x1000>; }; eth: ethernet@15100000 {