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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id x16sm313775ejo.104.2020.12.02.06.06.20 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:20 -0800 (PST) Sender: Michal Simek From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Cc: Anurag Kumar Vulisha , Krzysztof Kozlowski , Rajan Vaja , Rob Herring , Venkatesh Yadav Abbarapu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/12] arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 Date: Wed, 2 Dec 2020 15:06:02 +0100 Message-Id: <679a09c15babcc6c209e5e6466a9fa76d1e2c271.1606917949.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable si5341 driver is the main chip for providing preprogrammed clocks for the whole platform. # cat /sys/kernel/debug/clk/clk_summary ... refhdmi 1 1 0 114285000 0 0 50000 xtal_0 0 0 0 114285000 0 0 50000 pll_0 0 0 0 40731174000000 0 0 50000 clk1_0 0 0 0 27000000 0 0 50000 clk0_0 0 0 0 27000000 0 0 50000 ref48M 1 2 0 48000000 0 0 50000 si5341 0 4 0 14000000 0 0 50000 clock-generator.N4 0 0 0 0 0 0 50000 clock-generator.N3 0 1 0 733260000 0 0 50000 clock-generator.9 0 1 0 33330000 0 0 50000 clock-generator.N2 0 1 0 104000000 0 0 50000 clock-generator.2 0 1 0 26000000 0 0 50000 clock-generator.N1 0 2 0 594000000 0 0 50000 clock-generator.7 0 1 0 74250000 0 0 50000 clock-generator.0 0 1 0 27000000 0 0 50000 clock-generator.N0 0 4 0 1000000000 0 0 50000 clock-generator.8 0 0 0 0 0 0 50000 clock-generator.6 0 1 0 125000000 0 0 50000 clock-generator.5 0 1 0 100000000 0 0 50000 clock-generator.4 0 1 0 100000000 0 0 50000 clock-generator.3 0 1 0 125000000 0 0 50000 clock-generator.1 0 0 0 0 0 0 50000 ... Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 56 ++++++++++++++++++- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 45 +++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 46 ++++++++++++++- 3 files changed, 145 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5ff7ab665374..68c2ad30d62d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -133,6 +133,13 @@ ina226-u75 { io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; @@ -489,9 +496,56 @@ i2c@1 { #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "silabs,si5341"; reg = <0x36>; - }; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_4: out@4 { + /* refclk4 for PS-GT, used for PCIE slot */ + reg = <4>; + always-on; + }; + si5341_5: out@5 { + /* refclk5 for PS-GT, used for PCIE */ + reg = <5>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_7: out@7 { + /* refclk7 PL CLK74 */ + reg = <7>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; + }; }; i2c@2 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7910ac125101..a29ff20090ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -133,6 +133,13 @@ ina226-u75 { io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; @@ -488,7 +495,45 @@ i2c@1 { #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_7: out@7 { + /* refclk7 PL CLK74 */ + reg = <7>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d9a8fdbbcae8..92b3cee62d11 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -116,6 +116,13 @@ ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; + + /* 48MHz reference crystal */ + ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; &dcc { @@ -374,9 +381,46 @@ i2c@1 { #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ + compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + clock-output-names = "si5341"; + + si5341_0: out@0 { + /* refclk0 for PS-GT, used for DP */ + reg = <0>; + always-on; + }; + si5341_2: out@2 { + /* refclk2 for PS-GT, used for USB3 */ + reg = <2>; + always-on; + }; + si5341_3: out@3 { + /* refclk3 for PS-GT, used for SATA */ + reg = <3>; + always-on; + }; + si5341_5: out@5 { + /* refclk5 PL CLK100 */ + reg = <5>; + always-on; + }; + si5341_6: out@6 { + /* refclk6 PL CLK125 */ + reg = <6>; + always-on; + }; + si5341_9: out@9 { + /* refclk9 used for PS_REF_CLK 33.3 MHz */ + reg = <9>; + always-on; + }; }; - }; i2c@2 { #address-cells = <1>;