From patchwork Sun Oct 23 03:21:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 78814 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp1989555qge; Sat, 22 Oct 2016 20:23:43 -0700 (PDT) X-Received: by 10.99.173.75 with SMTP id y11mr13423335pgo.130.1477193023091; Sat, 22 Oct 2016 20:23:43 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id to9si7749502pab.33.2016.10.22.20.23.42; Sat, 22 Oct 2016 20:23:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935604AbcJWDXl (ORCPT + 7 others); Sat, 22 Oct 2016 23:23:41 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:53420 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964905AbcJWDXl (ORCPT ); Sat, 22 Oct 2016 23:23:41 -0400 Received: from 172.24.1.137 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.137]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DPI28856; Sun, 23 Oct 2016 11:21:19 +0800 (CST) Received: from [127.0.0.1] (10.177.23.32) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Sun, 23 Oct 2016 11:21:17 +0800 To: Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland CC: Scott Wood , , Shawn Guo , , From: Ding Tianhong Subject: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum Message-ID: <962ea92f-870b-e1d0-5bb7-1a6d66c35122@huawei.com> Date: Sun, 23 Oct 2016 11:21:10 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Ding Tianhong --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ef5fbe9..26bc837 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of + QorIQ erratum 161201, which says that reading the counter is + unreliable unless the small range of value is returned by back-to-back reads. + This also affects writes to the tval register, due to the implicit + counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize