From patchwork Tue Feb 11 03:21:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 204947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE5C9C35242 for ; Tue, 11 Feb 2020 03:22:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8A2F720661 for ; Tue, 11 Feb 2020 03:22:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="EnBQ14yM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728011AbgBKDWX (ORCPT ); Mon, 10 Feb 2020 22:22:23 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:10991 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728010AbgBKDWI (ORCPT ); Mon, 10 Feb 2020 22:22:08 -0500 X-UUID: 8771a79ea72b4bebbfa993842887e7a7-20200211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=r8ejWidlqTJxz08EZdYATpK/d/uKxpmz1wmwhDhD88A=; b=EnBQ14yM6GCiVgbkRUipum8S2QWgzbzNL2uFXJjXEcvgpwGHM5in8Wsj2lA9nDPuG2o3h9kfUnltUJhJsIBLgzE/7hef0EnSpPPsItImnStK7/72T8N0lsB55QbScprsXxo6ihqmBz4k0IMs656dTXrWFW/6fGub4ZPUZ6LnfCg=; X-UUID: 8771a79ea72b4bebbfa993842887e7a7-20200211 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1590352609; Tue, 11 Feb 2020 11:21:53 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 11 Feb 2020 11:20:24 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 11 Feb 2020 11:20:57 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Rob Herring , Mark Rutland , Matthias Brugger , , Chunfeng Yun , , , Subject: [RESEND PATCH v5 04/11] dt-bindings: phy-mtk-tphy: add a new reference clock Date: Tue, 11 Feb 2020 11:21:09 +0800 Message-ID: X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: References: MIME-Version: 1.0 X-TM-SNTS-SMTP: C7BF73084191A2E385A32F298866C72CB013C6A40172E1BF65CF20618662C3962000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Usually the digital and analog phys use the same reference clock, but on some platforms, they are separated, so add another optional clock to support it. In order to keep the clock names consistent with PHY IP's, use the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun Acked-by: Rob Herring --- v4~v5: no changes v3: add acked-by Rob v2: fix typo of analog and needed --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.25.0 diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 48bc1a2e9299..a859b0db4051 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -41,9 +41,12 @@ Optional properties (PHY_TYPE_USB2 port (child) node): - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : may contain - "ref": 48M reference clock for HighSpeed anolog phy; and 26M - reference clock for SuperSpeed anolog phy, sometimes is + "ref": 48M reference clock for HighSpeed (digital) phy; and 26M + reference clock for SuperSpeed (digital) phy, sometimes is 24M, 25M or 27M, depended on platform. + "da_ref": the reference clock of analog phy, used if the clocks + of analog and digital phys are separated, otherwise uses + "ref" clock only if needed. - mediatek,eye-src : u32, the value of slew rate calibrate - mediatek,eye-vrt : u32, the selection of VRT reference voltage