| Message ID | cf4ced33cb7dc8d43b79bb9d4ad6acd3b8ecc09b.1683034376.git.michal.simek@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: zynqmp: Misc zynqmp changes | expand |
Hi Michal, Thank you for the patch. On Tue, May 02, 2023 at 03:35:33PM +0200, Michal Simek wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for > CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache > node and let each CPU point to it. The commit message should focus on how this change brings the DT in line with the hardware, not on what the Linux kernel does. > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index bb0d0be30aa0..c2d80c7967e9 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -33,6 +33,7 @@ cpu0: cpu@0 { > operating-points-v2 = <&cpu_opp_table>; > reg = <0x0>; > cpu-idle-states = <&CPU_SLEEP_0>; > + next-level-cache = <&L2>; > }; > > cpu1: cpu@1 { > @@ -42,6 +43,7 @@ cpu1: cpu@1 { > reg = <0x1>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP_0>; > + next-level-cache = <&L2>; > }; > > cpu2: cpu@2 { > @@ -51,6 +53,7 @@ cpu2: cpu@2 { > reg = <0x2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP_0>; > + next-level-cache = <&L2>; > }; > > cpu3: cpu@3 { > @@ -60,6 +63,12 @@ cpu3: cpu@3 { > reg = <0x3>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP_0>; > + next-level-cache = <&L2>; > + }; > + > + L2: l2-cache { Shouldn't labels be lower-case ? > + compatible = "cache"; > + cache-level = <2>; > }; > > idle-states {
Hi Laurent, On 5/10/23 08:57, Laurent Pinchart wrote: > Hi Michal, > > Thank you for the patch. > > On Tue, May 02, 2023 at 03:35:33PM +0200, Michal Simek wrote: >> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> >> Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for >> CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache >> node and let each CPU point to it. > > The commit message should focus on how this change brings the DT in line > with the hardware, not on what the Linux kernel does. ok. > >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> Signed-off-by: Michal Simek <michal.simek@amd.com> >> --- >> >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> index bb0d0be30aa0..c2d80c7967e9 100644 >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> @@ -33,6 +33,7 @@ cpu0: cpu@0 { >> operating-points-v2 = <&cpu_opp_table>; >> reg = <0x0>; >> cpu-idle-states = <&CPU_SLEEP_0>; >> + next-level-cache = <&L2>; >> }; >> >> cpu1: cpu@1 { >> @@ -42,6 +43,7 @@ cpu1: cpu@1 { >> reg = <0x1>; >> operating-points-v2 = <&cpu_opp_table>; >> cpu-idle-states = <&CPU_SLEEP_0>; >> + next-level-cache = <&L2>; >> }; >> >> cpu2: cpu@2 { >> @@ -51,6 +53,7 @@ cpu2: cpu@2 { >> reg = <0x2>; >> operating-points-v2 = <&cpu_opp_table>; >> cpu-idle-states = <&CPU_SLEEP_0>; >> + next-level-cache = <&L2>; >> }; >> >> cpu3: cpu@3 { >> @@ -60,6 +63,12 @@ cpu3: cpu@3 { >> reg = <0x3>; >> operating-points-v2 = <&cpu_opp_table>; >> cpu-idle-states = <&CPU_SLEEP_0>; >> + next-level-cache = <&L2>; >> + }; >> + >> + L2: l2-cache { > > Shouldn't labels be lower-case ? Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:220: L2_0: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:241: L2_100: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:257: L2_200: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:273: L2_300: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:289: L2_400: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:305: L2_500: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:321: L2_600: l2-cache { Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml:337: L2_700: l2-cache { Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml:116: L2_0: l2-cache { Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml:151: L2_1: l2-cache { Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml:77: L2_0: l2-cache { And in dt spec - 6.2 chapter uppercase letter is valid chars for DTS labels. Thanks, Michal
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index bb0d0be30aa0..c2d80c7967e9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -33,6 +33,7 @@ cpu0: cpu@0 { operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ cpu1: cpu@1 { reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ cpu2: cpu@2 { reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,12 @@ cpu3: cpu@3 { reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; idle-states {