From patchwork Wed Dec 21 00:02:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B4EAC4167B for ; Wed, 21 Dec 2022 00:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234004AbiLUADA (ORCPT ); Tue, 20 Dec 2022 19:03:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229943AbiLUAC7 (ORCPT ); Tue, 20 Dec 2022 19:02:59 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43D161C900; Tue, 20 Dec 2022 16:02:58 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id h16so13390292wrz.12; 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Tue, 20 Dec 2022 16:02:56 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:56 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 0/9] Add IRQC support to RZ/G2UL SoC Date: Wed, 21 Dec 2022 00:02:33 +0000 Message-Id: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Hi All, This patch series does the following: * Adds IRQC support to the RZ/G2UL SoC. * Drops mapping NMI interrupt as part of IRQ domain * Parses interrupts based in interrupt-names * Includes a fix for pinctrl driver when using GPIO pins as interrupts * Adds PHY interrupt support for ETH{0/1} v1->v2 * Updated binding doc * Dropped mapping NMI interrupt as part of IRQ domain * Fixed review comments pointed by Geert * Added support to parse interrupts by name * Added compile time checks for gpio config arrays RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (9): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC dt-bindings: interrupt-controller: irqc-rzg2l: Drop RZG2L_NMI macro irqchip: irq-renesas-rzg2l: Skip mapping NMI interrupt as part of hierarchy domain irqchip: irq-renesas-rzg2l: Add support for RZ/G2UL SoC pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks arm64: dts: renesas: r9a07g043u: Add IRQC node arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} .../renesas,rzg2l-irqc.yaml | 240 +++++++++++++----- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 + arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++++ .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +- drivers/irqchip/irq-renesas-rzg2l.c | 102 ++++++-- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +- .../interrupt-controller/irqc-rzg2l.h | 3 - 7 files changed, 366 insertions(+), 89 deletions(-)