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[0/2] gpio: ixp4xx: Handle external clock output

Message ID 20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org
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Series gpio: ixp4xx: Handle external clock output | expand

Message

Linus Walleij Sept. 20, 2023, 10:23 p.m. UTC
The GPIO block on the very legacy IXP4xx GPIO can provide
a generated clock output on GPIO 14 and GPIO 15. This
provides a straight-forward solution with a flag for each
clock output.

More complicated solutions are thinkable, but I deemed them
overdesigned for this legacy SoC.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Linus Walleij (2):
      gpio: Rewrite IXP4xx GPIO bindings in schema
      gpio: ixp4xx: Handle clock output on pin 14 and 15

 .../devicetree/bindings/gpio/intel,ixp4xx-gpio.txt | 38 ------------
 .../bindings/gpio/intel,ixp4xx-gpio.yaml           | 70 ++++++++++++++++++++++
 MAINTAINERS                                        |  2 +-
 drivers/gpio/gpio-ixp4xx.c                         | 36 ++++++++++-
 4 files changed, 106 insertions(+), 40 deletions(-)
---
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
change-id: 20230921-ixp4xx-gpio-clocks-7e82289f4bb3

Best regards,

Comments

Rob Herring Sept. 21, 2023, 6:44 p.m. UTC | #1
On Thu, Sep 21, 2023 at 12:23:45AM +0200, Linus Walleij wrote:
> This rewrites the IXP4xx GPIO bindings to use YAML schema,
> and adds two new properties to enable fixed clock output on
> pins 14 and 15.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  .../devicetree/bindings/gpio/intel,ixp4xx-gpio.txt | 38 ------------
>  .../bindings/gpio/intel,ixp4xx-gpio.yaml           | 70 ++++++++++++++++++++++
>  MAINTAINERS                                        |  2 +-
>  3 files changed, 71 insertions(+), 39 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
> deleted file mode 100644
> index 8dc41ed99685..000000000000
> --- a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -Intel IXP4xx XScale Networking Processors GPIO
> -
> -This GPIO controller is found in the Intel IXP4xx processors.
> -It supports 16 GPIO lines.
> -
> -The interrupt portions of the GPIO controller is hierarchical:
> -the synchronous edge detector is part of the GPIO block, but the
> -actual enabling/disabling of the interrupt line is done in the
> -main IXP4xx interrupt controller which has a 1:1 mapping for
> -the first 12 GPIO lines to 12 system interrupts.
> -
> -The remaining 4 GPIO lines can not be used for receiving
> -interrupts.
> -
> -The interrupt parent of this GPIO controller must be the
> -IXP4xx interrupt controller.
> -
> -Required properties:
> -
> -- compatible : Should be
> -  "intel,ixp4xx-gpio"
> -- reg : Should contain registers location and length
> -- gpio-controller : marks this as a GPIO controller
> -- #gpio-cells : Should be 2, see gpio/gpio.txt
> -- interrupt-controller : marks this as an interrupt controller
> -- #interrupt-cells : a standard two-cell interrupt, see
> -  interrupt-controller/interrupts.txt
> -
> -Example:
> -
> -gpio0: gpio@c8004000 {
> -	compatible = "intel,ixp4xx-gpio";
> -	reg = <0xc8004000 0x1000>;
> -	gpio-controller;
> -	#gpio-cells = <2>;
> -	interrupt-controller;
> -	#interrupt-cells = <2>;
> -};
> diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml
> new file mode 100644
> index 000000000000..bb1fc393bd8c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel IXP4xx XScale Networking Processors GPIO Controller
> +
> +description: This GPIO controller is found in the Intel IXP4xx
> +  processors. It supports 16 GPIO lines.
> +  The interrupt portions of the GPIO controller is hierarchical.
> +  The synchronous edge detector is part of the GPIO block, but the
> +  actual enabling/disabling of the interrupt line is done in the
> +  main IXP4xx interrupt controller which has a 1-to-1 mapping for
> +  the first 12 GPIO lines to 12 system interrupts.
> +  The remaining 4 GPIO lines can not be used for receiving
> +  interrupts.
> +  The interrupt parent of this GPIO controller must be the
> +  IXP4xx interrupt controller.
> +  GPIO 14 and 15 can be used as clock outputs rather than GPIO,
> +  and this can be enabled by a special flag.

Do you care about the formatting here? If so, you are missing a '|'. If 
not, you have strange line breaks.

> +
> +maintainers:
> +  - Linus Walleij <linus.walleij@linaro.org>
> +
> +properties:
> +  compatible:
> +    const: intel,ixp4xx-gpio
> +
> +  reg:
> +    maxItems: 1
> +
> +  gpio-controller: true

Blank line between DT properties

> +  "#gpio-cells":
> +    const: 2
> +
> +  interrupt-controller: true

Blank line

> +  "#interrupt-cells":
> +    const: 2

Otherwise, with those nits fixed:

Reviewed-by: Rob Herring <robh@kernel.org>