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[0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

Message ID 20241212-correct_gpio_ranges-v1-0-c5f20d61882f@quicinc.com
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Series Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 | expand

Message

Lijuan Gao Dec. 12, 2024, 9:23 a.m. UTC 
The UFS_RESET pin is expected to be wired to the reset pin of the
primary UFS memory, it's a general purpose output pin. Reorder it and
expose it as a gpio, so that the UFS driver can toggle it.

The QCS615 TLMM pin controller has GPIOs 0-122, so correct the
gpio-rangs to 124.

The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
gpio-rangs to 134.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
Lijuan Gao (6):
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
      pinctrl: qcom: correct the number of ngpios for QCS615
      pinctrl: qcom: correct the number of ngpios for QCS8300
      arm64: dts: qcom: correct gpio-ranges for QCS615
      arm64: dts: qcom: correct gpio-ranges for QCS8300

 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
 arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7

Best regards,

Comments

Dmitry Baryshkov Dec. 12, 2024, 9:34 a.m. UTC | #1 
On Thu, Dec 12, 2024 at 05:23:59PM +0800, Lijuan Gao wrote:
> The UFS_RESET pin is expected to be wired to the reset pin of the
> primary UFS memory, it's a general purpose output pin. Reorder it and
> expose it as a gpio, so that the UFS driver can toggle it.

I don't see pins being reordered. Please correct your commit messages.

> 
> The QCS615 TLMM pin controller has GPIOs 0-122, so correct the
> gpio-rangs to 124.
> 
> The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
> Lijuan Gao (6):
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
>       pinctrl: qcom: correct the number of ngpios for QCS615
>       pinctrl: qcom: correct the number of ngpios for QCS8300
>       arm64: dts: qcom: correct gpio-ranges for QCS615
>       arm64: dts: qcom: correct gpio-ranges for QCS8300
> 
>  Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
>  Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
>  arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
>  drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
>  drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
>  6 files changed, 6 insertions(+), 6 deletions(-)
> ---
> base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
> change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7
> 
> Best regards,
> -- 
> Lijuan Gao <quic_lijuang@quicinc.com>
>