From patchwork Wed Dec 21 00:02:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6125C4167B for ; Wed, 21 Dec 2022 00:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234291AbiLUADD (ORCPT ); Tue, 20 Dec 2022 19:03:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbiLUADA (ORCPT ); Tue, 20 Dec 2022 19:03:00 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B3DD1EEF0; Tue, 20 Dec 2022 16:02:59 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id co23so13445084wrb.4; Tue, 20 Dec 2022 16:02:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3bwX/rCMg/rUB7jj3GnuFZ4IZO0Zw8FzaOg+ESeEo9Q=; b=b1OTjaIpk+JKeoGTM68BP+sJYMuxNLAiS/4/0W8Y9v8rSqQAbRbNyqvc6CWeufDGSn 3tEnRaU1MS+V2jGeVf3mzQ49wr1wS6c6s5z3qL6hENcAUStc8C8nAeG05/BzwvDjxLGh 9CJ5sQOHvt5SLNgZMPx9/CCureWQmfnfigZEAOz4KC5Z2l19ijZeGYsgktJHiZCHwwBE D5qRUB0AxFIT3Jmg4HQluy+6uMMphzy5Erd2Lqgma/7NV6Js5hWHVVMIvNJR8eJF5UCA f4S9VE3nSClAid77RcqIRi+3IDzh80XQPXOCFG+VpPcQyliyKUJIYhT8tEZ5zxAL+ARF afxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3bwX/rCMg/rUB7jj3GnuFZ4IZO0Zw8FzaOg+ESeEo9Q=; b=Z5yUGP25S5nGRuVBi0XVGXuUpsZblLQIhWsB7HqLrU4P481xrG8fPh+k9zarcpwUQG bI0G2jbptFHRfRXH/jFelQqkMeL23eUCs1ISWWiqBVoVCUnN6HGMb/p4BcSNoLkHuLxC /srotJosl6g1i9Cj3wFWuo2pSl5EIwQG05dDLG7YSe3ddT+sVXLAXaM5iPvSaMUz3XLj u0WpuMs4m0N7YYEZl2tn3riprxa+2IN4i1nEpXwB5u0Kzsg3Bw/JzKZjmbyCf9BC4Epn q+i5kCkWqrn2WdRhGHUNuTjySfEip4zv3bpoUGyXQAjTfU9lHHkO1FclzK/PWWm+Vwsf GXkw== X-Gm-Message-State: ANoB5pm0bCnMp4+hA4N/Bet2dqGyFbfKbxSOLnp0uRA3n/VhW/jQRtFl ldYhxv7IymDQSP992FTmM9A= X-Google-Smtp-Source: AA0mqf5jTQZpZ8O5ZfcmE8bSLLb/W6heJH9CKxlFPiwUk8slEhmpBai+Py3peAbF+n4kSZdZQaKEmA== X-Received: by 2002:a05:6000:1e16:b0:242:8177:62a3 with SMTP id bj22-20020a0560001e1600b00242817762a3mr44829407wrb.21.1671580977687; Tue, 20 Dec 2022 16:02:57 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:57 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas, rzg2l-irqc: Document RZ/G2UL SoC Date: Wed, 21 Dec 2022 00:02:34 +0000 Message-Id: <20221221000242.340202-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. Hence new generic compatible string "renesas,rzg2ul-irqc" is added for RZ/G2UL SoC. Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC interrupt-names property is added so that we can parse them based on names. While at it updated the example node to four spaces and added interrupt-names property. Signed-off-by: Lad Prabhakar --- v1- > v2 * Dropped RB tags * Added generic compatible string for rzg2ul * Added interrupt-names * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names * Updated example node with interrupt-names * Used 4 spaces for example node --- .../renesas,rzg2l-irqc.yaml | 240 +++++++++++++----- 1 file changed, 180 insertions(+), 60 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index 33b90e975e33..6a0cf57698ab 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -19,16 +19,19 @@ description: | - NMI edge select (NMI is not treated as NMI exception and supports fall edge and stand-up edge detection interrupts) -allOf: - - $ref: /schemas/interrupt-controller.yaml# - properties: compatible: - items: - - enum: - - renesas,r9a07g044-irqc # RZ/G2{L,LC} - - renesas,r9a07g054-irqc # RZ/V2L - - const: renesas,rzg2l-irqc + oneOf: + - items: + - enum: + - renesas,r9a07g044-irqc # RZ/G2{L,LC} + - renesas,r9a07g054-irqc # RZ/V2L + - const: renesas,rzg2l-irqc + + - items: + - enum: + - renesas,r9a07g043u-irqc # RZ/G2UL + - const: renesas,rzg2ul-irqc '#interrupt-cells': description: The first cell should contain external interrupt number (IRQ0-7) and the @@ -44,7 +47,96 @@ properties: maxItems: 1 interrupts: - maxItems: 41 + minItems: 41 + items: + - description: NMI interrupt + - description: IRQ0 interrupt + - description: IRQ1 interrupt + - description: IRQ2 interrupt + - description: IRQ3 interrupt + - description: IRQ4 interrupt + - description: IRQ5 interrupt + - description: IRQ6 interrupt + - description: IRQ7 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Bus error interrupt + + interrupt-names: + minItems: 41 + items: + - const: nmi + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: bus-err clocks: maxItems: 2 @@ -72,6 +164,23 @@ required: - power-domains - resets +allOf: + - $ref: /schemas/interrupt-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,rzg2ul-irqc + then: + properties: + interrupts: + minItems: 42 + interrupt-names: + minItems: 42 + required: + - interrupt-names + unevaluatedProperties: false examples: @@ -80,55 +189,66 @@ examples: #include irqc: interrupt-controller@110a0000 { - compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; - reg = <0x110a0000 0x10000>; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, - <&cpg CPG_MOD R9A07G044_IA55_PCLK>; - clock-names = "clk", "pclk"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_IA55_RESETN>; + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg = <0x110a0000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31"; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; };