| Message ID | 20240606125755.53778-2-i@eh5.me |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: rockchip: fix RK3328 pinmux bits | expand |
Am Donnerstag, 6. Juni 2024, 14:57:52 CEST schrieb Huang-Huang Bao: > The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, > correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is > recalculated so it remain unchanged. > > The pinmux bits for those pins are not explicitly specified in RK3328 > TRM, however we can get hint from pad name and its correspinding IOMUX > setting for pins in interface descriptions. The correspinding IOMIX > settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to > occurrences of following pad names in RK3328 TRM. > > GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5 > GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5 > GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5 > GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5 > GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5 > GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5 > GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5 > > This fix has been tested on NanoPi R2S for fixing confliting pinmux bits > between GPIO2-B7 with GPIO2-B5. > > Signed-off-by: Huang-Huang Bao <i@eh5.me> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") The TRM also supports those findings, as gpio2-b4 actually is documented there as 2-bit wide with the functions you found in the pad descriptions.
Hi Huang-Huang, Heiko, all four patches applied for fixes! Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 3bedf36a0019..78dcf4daccde 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -634,12 +634,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { .num = 2, .pin = 15, .reg = 0x28, @@ -3763,7 +3757,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + 0, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is recalculated so it remain unchanged. The pinmux bits for those pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions. The correspinding IOMIX settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to occurrences of following pad names in RK3328 TRM. GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5 GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5 GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5 GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5 GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5 GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5 GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5 This fix has been tested on NanoPi R2S for fixing confliting pinmux bits between GPIO2-B7 with GPIO2-B5. Signed-off-by: Huang-Huang Bao <i@eh5.me> --- drivers/pinctrl/pinctrl-rockchip.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)