From patchwork Mon Sep 23 10:06:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 830379 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67A861993BB; Mon, 23 Sep 2024 10:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727085988; cv=none; b=GD4wcesZwr72bVh00SAS3d147bgjsIgb406Or9/B/uosmpn75FAwA55OnWRz6uqR/vFpUchoxu7rxL6ZJG5McJVP1wuQoOzapyO6pCpVozeBw6hoZoLIOaQhBXL3vHgHUkPpPySY9vA6HwasGTb+FLIEBlgnCN8lukcVpkae31I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727085988; c=relaxed/simple; bh=+SF2U+LpVfShsw5rPXRF+45BmwlrtgSmhhRLX7i3zf4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GMltNksX9v4Phf7ZaDwoUUYOFCbdtS4q4AA4NgT897kBFN3mFdlZDCnWlLl6vd4GhILnqoq4d6U/BPqLXkf41WStgubGrIPLsacLLTuciJbzNCFrJp7Ws6tT8UdZ3FMaw8BEfSJ+wRVhxzf4snrSMvRjM20y5nKv+e820f4qHrM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 23 Sep 2024 18:06:12 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 23 Sep 2024 18:06:12 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v5 6/6] gpio: aspeed: Add the flush write to ensure the write complete. Date: Mon, 23 Sep 2024 18:06:11 +0800 Message-ID: <20240923100611.1597113-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240923100611.1597113-1-billy_tsai@aspeedtech.com> References: <20240923100611.1597113-1-billy_tsai@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO's high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 230af90aa966..e7dcc37e40f9 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -402,6 +402,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, struct aspeed_gpio *gpio = gpiochip_get_data(gc); gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bit_get(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,