From patchwork Tue May 27 05:23:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 892845 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08CEF1D9694; Tue, 27 May 2025 05:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; cv=none; b=fm4uFyWhza5JwWcZlqFAhpjOVK6Vma2PLKtK4MbVgOgcggc5ylkGv1+cfWTv6RIH3klquYYN8PzUTD0dseTL2CFQ/BQEUEyJEvtaBzXqY+vno3BlI0ZIdvnP5/MjRThmSnC8VD3Mymv+fKoOgJA6+adikl9W96ObUHOHvO7Ojrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748323411; c=relaxed/simple; bh=Hj/dtiodyDNGd1NBE4jDypDZMQYKxKPm40P5Dg7K4HU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UKCFVbgLa4G21l30PGxnnE9ynq0zYluOksv4pgHqHjvR5xDH4yHMsFTq9fD0pk9PQndYFQ1D8rxdDsjaTq76T7CgjBUXM19oKhNZWD3mZAQ/y2JuB019KQ3Xm7z/Lfbd0h3Ilzem9yQ4jpsrjoLJ/gRii9IqGVbehQ4spDccq4U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=at9BQojQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="at9BQojQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8C362C4CEF4; Tue, 27 May 2025 05:23:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748323410; bh=Hj/dtiodyDNGd1NBE4jDypDZMQYKxKPm40P5Dg7K4HU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=at9BQojQQ1CziglvVbY08cY/jvGczUfphMoTDMnTSK9TF0igOCHaYLZDUMdiOd3tE gyGUBeNC9Q0JkDZEYG0qCqrgg2Jr4CvCVDUyL156ilAJjL3pmaB/4rLRMjnsnAe4ov dfTAyYUXSp60uaCYyD+veZMUFLLTspcorXB2OD7L7FBawoXaleyYHYFwp6bNJhrODJ Mt6VnE6nM7HlV6R8aq3XdVJbEqtwH3I+Y2KnZaX3p78xe2jPphEjoLcvIJiGKrtQOm b0AmdzTKSx+mIJCm/h2gfWVloMQOARg3WX8cXnNu9q237kUSjFM+0s25tnDd2Nekqy xwPdv1V7JgVSg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80364C5B54C; Tue, 27 May 2025 05:23:30 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 27 May 2025 13:23:31 +0800 Subject: [PATCH v3 4/6] dts: arm64: amlogic: add S7 pinctrl node Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250527-s6-s7-pinctrl-v3-4-44f6a0451519@amlogic.com> References: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> In-Reply-To: <20250527-s6-s7-pinctrl-v3-0-44f6a0451519@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748323408; l=3129; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=fjCfY1jseWaBwy2ltob7mgikXcrVQkc9RawMyG1Dk4I=; b=jnjPYxx6pXHnNqyMHAeUGarOwFUnBZYF2rZNSfJtfL2cj5yqrwhjxnK2nj8mD3Z0FGMJhIqfS WERrdJEV4EPChQo3aLSXYF8ZlkDZnEhEufcezhjZqW+PkcybR0ol1p3 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index f0c172681bd1..260918b37b9a 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { @@ -94,6 +95,86 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,pinctrl-s7"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>; + }; + + gpioe: gpio@1c0 { + reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + test_n: gpio@2c0 { + reg = <0 0x2c0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; };