From patchwork Fri Jun 13 03:29:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 896320 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66880254848; Fri, 13 Jun 2025 03:30:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785414; cv=none; b=e0Bi7KEMA7RHrTtWM0/smU5S9Ba+lhhEabDy6XY0c7hN9WBvSlUpv+8spsm7t6O12Zd3ZksYP1kMu7gvNOAlF1A9JuU1/XPichEt6NQCFZ85apfWuHGRQxpS6kHnMwhtblXSWt1w62v2aFvk1bs7BJiPqsnzFsa+fLGaHChxOM0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785414; c=relaxed/simple; bh=EGiB6GhHKp3e43IlMi785J2K2HQxD+KwUnb+1OiJQ0s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HH2ZynnSf9wNXur/AWRcUn5YwcEp1cDeoWVsSeesCl1IHiNvjdrUs1Jg3xWNfomn73c8seqT0oQMwq+RkR8hOaXo1ln5EpkufZJfI5YCtcWyw3qmH65/mPETIIJyNBmfGe7R+g9e7TjKkSZbisSxUZtwhWh9iPyVvtlQrzzUr7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Jun 2025 11:30:02 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Jun 2025 11:30:02 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Date: Fri, 13 Jun 2025 11:29:57 +0800 Message-ID: <20250613033001.3153637-4-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add device tree binding documentation for the ASPEED PCIe Root Complex controller. This binding describes the required and optional properties for configuring the PCIe RC node, including support for syscon phandles, MSI, clocks, resets, and interrupt mapping. The schema enforces strict property validation and provides a comprehensive example for reference. Signed-off-by: Jacky Chou --- .../devicetree/bindings/pci/aspeed-pcie.yaml | 159 ++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml new file mode 100644 index 000000000000..5b50a9e2d472 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/aspeed-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe Root Complex Controller + +maintainers: + - Jacky Chou + +description: | + Device tree binding for the ASPEED PCIe Root Complex controller. + +properties: + compatible: + enum: + - aspeed,ast2600-pcie + - aspeed,ast2700-pcie + + device_type: + const: pci + + reg: + maxItems: 1 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + description: IntX and MSI interrupt + + resets: + items: + - description: Module reset + - description: PCIe PERST + + reset-names: + items: + - const: h2x + - const: perst + + msi-parent: true + + msi_address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: MSI address + + aspeed,ahbc: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to ASPEED AHBC syscon. + + aspeed,pciecfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to ASPEED PCIe configuration syscon. + + aspeed,pciephy: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to ASPEED PCIe PHY syscon. + + clocks: + description: PCIe BUS clock + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - if: + properties: + compatible: + contains: + const: aspeed,ast2600-pcie + then: + required: + - aspeed,ahbc + +required: + - interrupts + - bus-range + - ranges + - resets + - reset-names + - msi-parent + - msi-controller + - aspeed,pciephy + - aspeed,pciecfg + - interrupt-map-mask + - interrupt-map + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include + #include + + apb { + #address-cells = <1>; + #size-cells = <1>; + + pcie0: pcie@1e7700C0 { + compatible = "aspeed,ast2600-pcie"; + device_type = "pci"; + reg = <0x1e7700C0 0x40>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x80 0xff>; + + ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; + + resets = <&syscon ASPEED_RESET_H2X>, + <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names = "h2x", "perst"; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcierc1_default>; + + #interrupt-cells = <1>; + msi-parent = <&pcie0>; + msi-controller; + msi_address = <0x1e77005C>; + + aspeed,ahbc = <&ahbc>; + aspeed,pciecfg = <&pciecfg>; + aspeed,pciephy = <&pcie_phy1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + };