From patchwork Sun Jun 15 01:12:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Harshit Shah X-Patchwork-Id: 897105 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2103.outbound.protection.outlook.com [40.107.92.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D4EC2E659; Sun, 15 Jun 2025 01:13:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.103 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749950010; cv=fail; b=ipM4Ns5BN4J8zldfR7OO/tbV+EnuiNqVWGnkw2gW4Wpq5pHuYus+N3RENAkhyfgdVp2mzUjZAAYC8xHab3geSHfmu4iuOgXm3jje/RYoTp5GjaKWqA0RSJEtxRckboi0PvuvyZE7Jfxm1h3QgrhVSXwQZr5W7rsbiJ5ANmq6O7k= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749950010; c=relaxed/simple; bh=ax5WVHwMn9h9/QI+fZ1jJWwNN4R6eLWVvY8XrQOgkgA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KEUSSxArIbpzgEOTjdp43sVX72jxfS+HwaPXGQ8e8NbTTJ/DjejQavEnmZ62uqKrpuvWCM5F6ENHb0JJ96nP7MC8tcQGb8H83X0irbwdKGe6zfyD8KqpQKBq7lidmANjgcxTDTKxlDPRpODDPAYwbl87l7x+ODgyyeM4lFMyeys= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=axiado.com; spf=pass smtp.mailfrom=axiado.com; dkim=pass (2048-bit key) header.d=axiado.com header.i=@axiado.com header.b=NeAYj8yc; arc=fail smtp.client-ip=40.107.92.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=axiado.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=axiado.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=axiado.com header.i=@axiado.com header.b="NeAYj8yc" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tN/BCqR5kuXK9ZduGsdQDAcTuWYDsuadKcSQvP5Msp1fksJVdhY4nco6jG1btBdq6wQBY4PaT/3Arq40GhBRr6lysYw2MB4aEpannb7lUwdRLJkoxh52GUKjX55Vjn5E77cAUL0B81aQGixlAFUQT80RA75l9MPmBSvqi3A9yq2qNX1nN5CLU6JKBUCShoAA/rL3x3ufwgnqIMJ53ShDR5DU9BHHLa0JUqXSK9ZargUg/qrtUM1TodzZ4AcHByA9jjhZAfgT+EJ/K4uBtTdvj5dG0G8bqtwq9wjEfL/OF91BxYWtFAWwDTr7ehfXsmmEWrNBjWrfU57oOcxtIXSUMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qTytpIyACWpdVOC1FrmEAlCiu3DOhyaJw9sL+z8P8t8=; b=o1dsaz5djm0ehsLkUB2sEBR1TEq2YF2j6R7zHy9jjGhy6hZaOQr98UwHqcAu8wZOJDR+64mxmXVoip7+oCFE/6MoH7Y0gsD8J2iyCoxQeWDmRDsv/mkxC6plv77Y2GVpw/vszDJCiebPKSdgdMFmrpNqSgftT63z+cp7fqafz39z90zN7evjUXRSJSLFkpm92IPKMbOYEbV4G1dIRq65L8gjlqv/98142K6g5t9hUIsQzJyHnBUAPQ6qiBjnfX+kdRmLnjN1BWWroOxGQ/haMVH/2Sk70W6bbIfAtCl5boIdQUEkeJktDBIxlzilDuryOWOTY0p4srkS4EQJl8bXQQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 50.233.182.194) smtp.rcpttodomain=arndb.de smtp.mailfrom=axiado.com; dmarc=none action=none header.from=axiado.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axiado.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qTytpIyACWpdVOC1FrmEAlCiu3DOhyaJw9sL+z8P8t8=; b=NeAYj8ycKnNqi+k7uyHqp5bySBhkTCyPZSnr7edduTCBJbnsPqhw+Ms6ouST4P5XaYs5jyfjZT5Ex4XAPOYCvkBGseQJp8Kr+Cj1CcpIOo4Gbb3kQVnZbViwc9JPGMZKXOaC2qALWhsDQqBsbYSQfX2fHCKGFi7f4eLkw1Hwbhod4y/4WBjavPlSZD4M7m3WR+SkL42/bXlOVDjsaDQR/qTAPixdLjouIeWkYKVUAgpWGnzdJ0n6Yl//3XTOLbjXb/liFuKQ0eGOyRVxvoSrFdV8eBnGwadCFoKRrtd9XIz4MitxcIr1Gk5rdEzezwADryNsTDIVuUtYS4wBKmtsuQ== Received: from BY3PR05CA0003.namprd05.prod.outlook.com (2603:10b6:a03:254::8) by SA0PR18MB3613.namprd18.prod.outlook.com (2603:10b6:806:71::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.28; Sun, 15 Jun 2025 01:13:20 +0000 Received: from MWH0EPF000989E7.namprd02.prod.outlook.com (2603:10b6:a03:254:cafe::2c) by BY3PR05CA0003.outlook.office365.com (2603:10b6:a03:254::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.18 via Frontend Transport; Sun, 15 Jun 2025 01:13:20 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 50.233.182.194) smtp.mailfrom=axiado.com; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=axiado.com; Received-SPF: Fail (protection.outlook.com: domain of axiado.com does not designate 50.233.182.194 as permitted sender) receiver=protection.outlook.com; client-ip=50.233.182.194; helo=[127.0.0.1]; Received: from [127.0.0.1] (50.233.182.194) by MWH0EPF000989E7.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.15 via Frontend Transport; Sun, 15 Jun 2025 01:13:19 +0000 From: Harshit Shah Date: Sat, 14 Jun 2025 18:12:50 -0700 Subject: [PATCH 4/6] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250614-axiado-ax3000-soc-and-evaluation-board-support-v1-4-327ab344c16d@axiado.com> References: <20250614-axiado-ax3000-soc-and-evaluation-board-support-v1-0-327ab344c16d@axiado.com> In-Reply-To: <20250614-axiado-ax3000-soc-and-evaluation-board-support-v1-0-327ab344c16d@axiado.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Arnd Bergmann , Catalin Marinas , Will Deacon Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Harshit Shah X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19004; i=hshah@axiado.com; h=from:subject:message-id; bh=ax5WVHwMn9h9/QI+fZ1jJWwNN4R6eLWVvY8XrQOgkgA=; b=owEB7QES/pANAwAKAfFYcxGhMtX7AcsmYgBoTh4o0x9p4+NoG2FMxsJ/4Jjs83ulZafOxJzTK oZWlB333mKJAbMEAAEKAB0WIQRO3pC/7SkLS2viWOvxWHMRoTLV+wUCaE4eKAAKCRDxWHMRoTLV +yFUC/9fwWsGhvYSWq/mAVKVfViHBjWa/oU/cSv9a/v0+tjPrdVAmfLB/oqUrmQXXFwXGkWFyQ5 5NQZBlppRKWFrlkGC1ykBSbcdprQA/AqC/ySwxf52ICkaugqv3caBG3SJGUi8aNrQ1Kf88H5DKP gBkG60DNlVbuMhyz31Bomlvl6xBcP69HQuCbZr9q/aQusUM6kwH4TO8cP98YKQqopJ6BOlI5a73 /6FrP39HMWy5KmLxnAkSfwWpC+21ff19qlSspor3VU3uyrAVlJmnropR9EIWzZrQgsl0mczElKP A2WdSg+Oc7D7GX1uq0wZsk7VC1LdNmCW/diore1Sx6VC0/7jLsTDtQkkBB0WUIUJIi9iKx08i3J Z1psT+FRojXRNmLTuZ7l3YAxJTVetAU5uMbzi5L7EhkzVu982eMDq1fu8oAzIvtSyo57cOMYicM kQfcHOzNV/olLXR9dzD+reEd+tjHpwlSl+jzel6fzohf6u6Za0VTsQm+g54zfEeX8wo0o= X-Developer-Key: i=hshah@axiado.com; a=openpgp; fpr=4EDE90BFED290B4B6BE258EBF1587311A132D5FB X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E7:EE_|SA0PR18MB3613:EE_ X-MS-Office365-Filtering-Correlation-Id: cc2a224d-330e-442c-1290-08ddaba9d128 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?PC1v9Pp6cuBCz1nPLE4O5woFSTehw8O?= =?utf-8?q?a1HRfAIehwFS3egbBUy69vmMQ7v1YETAdSzYgemvKRETR3B38ihwfHG5T03R2C+FU?= =?utf-8?q?2bIMlSGDUFYoAv1FWpkL3sk+4JlYVi7PdRhLwTJjRU/3opB/Ltt0xhsTih2KDHaPC?= =?utf-8?q?gqRzCs7ZKxFbedqRtMTzlR/Bzc4lG80bpDR+QWeH2Ax0JYTXrkNkdXN20E0naB75j?= =?utf-8?q?knT8R7VezaNhHGNOWah9ch/CmobSiY2wVf1/rnRAS8p733HNDbt1p700csMA8FwU2?= =?utf-8?q?mzE5E1N35birCl03DTb8izASL5mbNjsowke1xDZm+eEUJwhT0mu6c6A5shhaXNDQb?= =?utf-8?q?XGOBm1MPvSU/kekoelGftR3vBX7Zf1qZW7cwYmft+1WIEsQBdjVvkmzX3jRaRup+C?= =?utf-8?q?ET7i5Z/ZtECDsFYJVTnhcyKWA3IFl4xR43DWUHOJ+EYPZfC4Pw2kRS9IaC6J7xfqK?= =?utf-8?q?mt7WkwPB2JgxRcvTDXecJh4sP0RpxKsv8ab7+fsDphG4AEt/xSNz1NghS26J9uNOP?= =?utf-8?q?p/9niILapJLVPnRrpykC4Vr3B2LHP+oz2RE7XdWt4UgAkkP0O03ZNzQFeu3JQftN1?= =?utf-8?q?Ueoz/6tsH/Z9QNBJdc3OxYzeUdvFGuBLwf3qQKGAnno7ARbA17qTwJinGrhKlmzgx?= =?utf-8?q?ryjulQipTUlq5kn5xnGJect1iJEXobOeIiD0bxkPDDs9VCDOSy0NcMqwQBSnGe8vH?= =?utf-8?q?EtOWuWVkxNXfNgb4mn5lB6DgAj1i6hf76TaA4mNoO1vR78JTAWy42A0r6yqR27qDy?= =?utf-8?q?aovfSkkc1eaTg+V2ljizm1tjulrgsE4/wevzOQkr7UKR32DQ2QIIk/GRve9K81IXf?= =?utf-8?q?HMUd45LmHy9YCPON0BF8Qd1oJrpJBkjlik6c+Ef6c8BPKO+iBbEv2hyd4CSilo9wt?= =?utf-8?q?blwuaOLU7TzDOB4MWuPViuL8MYy7n+Mwl27LEMwiViCEg1awmOS4cwgVHOER0cLpB?= =?utf-8?q?Y0l/RLrSAeLYk9gFiPfhdNSPn43tYyA9ypdwI+Ge+3uX5O4IruNWm7hJr9ZKQJyF9?= =?utf-8?q?EP1SnNZT3ObtEhl9pmWUB4DVAX5/FGglSAaJo8tmGVxAiAeXM19m7m9LTmnumqcd+?= =?utf-8?q?yC1X8MNDWtEE7B0zubYkHtAQE8d0GpcQwX0Lu6qNHwouVPEjyZXLQZFEOicGMKOHy?= =?utf-8?q?gdLOOcgfTC8spAatMn6EjiIDVa27oiBHAZ/Gi8PfLBg50gtS5arnQb7hZjhH89B0C?= =?utf-8?q?oIXS0kqU7wvsrPTKCO+VzReBAFiEkvOO0v8ZHoQwWPE8bU90gKEid4VgBq+78WgcI?= =?utf-8?q?mLwSfjY4M+oW/nileSOpOomQu92G604U2ldMU+jEgsTQSudb9GF+OtoDYn5vfWxor?= =?utf-8?q?erWVxwMVL/Ad+VP23Rqg/K8YNM7pLPyntugrZVokIjNx4zLVEzl9p00bozs829DoI?= =?utf-8?q?90N8wRruDSYqT3ugpibS9oThcwbIoO5zPi8anvvrHBDWxUwp5Ncg7git+mMOKxefT?= =?utf-8?q?Y1dsevQepj?= X-Forefront-Antispam-Report: CIP:50.233.182.194; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:[127.0.0.1]; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(7416014)(376014); DIR:OUT; SFP:1102; X-OriginatorOrg: axiado.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2025 01:13:19.9416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc2a224d-330e-442c-1290-08ddaba9d128 X-MS-Exchange-CrossTenant-Id: ff2db17c-4338-408e-9036-2dee8e3e17d7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=ff2db17c-4338-408e-9036-2dee8e3e17d7; Ip=[50.233.182.194]; Helo=[[127.0.0.1]] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR18MB3613 Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores, Secure Vault, AI Engine and Firewall. This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C controllers on the AX3000 evaluation board. Signed-off-by: Harshit Shah --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/axiado/Makefile | 2 + arch/arm64/boot/dts/axiado/ax3000.dtsi | 584 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/axiado/ax3000_evk.dts | 72 ++++ 4 files changed, 659 insertions(+) diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y += amlogic subdir-y += apm subdir-y += apple subdir-y += arm +subdir-y += axiado subdir-y += bitmain subdir-y += blaize subdir-y += broadcom diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..eb5e08ba0f39c32cdbfd586d982849a80da30160 --- /dev/null +++ b/arch/arm64/boot/dts/axiado/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d5d84986d18efe9dfbb446ceee42fc4e4dbf95d0 --- /dev/null +++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved. + */ + +/dts-v1/; + +#include +#include + +/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */ +/ { + compatible = "axiado,ax3000"; + interrupt-parent = <&gic500>; + + aliases { + i3c0 = &i3c0; + i3c1 = &i3c1; + i3c2 = &i3c2; + i3c3 = &i3c3; + i3c4 = &i3c4; + i3c5 = &i3c5; + i3c6 = &i3c6; + i3c7 = &i3c7; + i3c8 = &i3c8; + i3c9 = &i3c9; + i3c10 = &i3c10; + i3c11 = &i3c11; + i3c12 = &i3c12; + i3c13 = &i3c13; + i3c14 = &i3c14; + i3c15 = &i3c15; + i3c16 = &i3c16; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x3c0013a0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x3c0013a0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x3c0013a0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x3c0013a0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x100000>; + cache-unified; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + }; + + timer:timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic500>; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + clocks { + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + ref_clk: ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1>; + }; + + clk_ahb: clk_ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_ahb"; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_xin"; + }; + + clk_mali: clk_mali { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + clock-output-names = "clk_mali"; + }; + + clk_pclk: clk_pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + clock-output-names = "clk_pclk"; + }; + + spi_clk: spi_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + apb_pclk: apb_pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + ranges; + + gic500: interrupt-controller@80300000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x00 0x80300000 0x00 0x10000>, + <0x00 0x80380000 0x00 0x80000>; + interrupts = ; + + }; + + uart0: serial@80520000 { + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + interrupt-parent = <&gic500>; + interrupts = ; + reg = <0x00 0x80520000 0x00 0x100>; + clock-names = "uart_clk", "pclk"; + clocks = <&refclk &refclk>; + status = "disabled"; + }; + + uart1: serial@805a0000 { + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + interrupt-parent = <&gic500>; + interrupts = ; + reg = <0x00 0x805A0000 0x00 0x100>; + clock-names = "uart_clk", "pclk"; + clocks = <&refclk &refclk>; + status = "disabled"; + }; + + uart2: serial@80620000 { + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + interrupt-parent = <&gic500>; + interrupts = ; + reg = <0x00 0x80620000 0x00 0x100>; + clock-names = "uart_clk", "pclk"; + clocks = <&refclk &refclk>; + status = "disabled"; + }; + + uart3: serial@80520800 { + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + interrupt-parent = <&gic500>; + interrupts = ; + reg = <0x00 0x80520800 0x00 0x100>; + clock-names = "uart_clk", "pclk"; + clocks = <&refclk &refclk>; + status = "disabled"; + }; + + /* GPIO Controller banks 0 - 7 */ + gpio0: gpio-controller@80500000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + reg = <0x00 0x80500000 0x00 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio-controller@80580000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80580000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio-controller@80600000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80600000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio3: gpio-controller@80680000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80680000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio4: gpio-controller@80700000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80700000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio5: gpio-controller@80780000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80780000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio6: gpio-controller@80800000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80800000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio7: gpio-controller@80880000 { + compatible = "cdns,gpio-r1p02"; + clocks = <&refclk>; + reg = <0x00 0x80880000 0x00 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + /* I3C Controller 0 - 16 */ + i3c0: i3c@80500400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80500400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c1: i3c@80500800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80500800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c2: i3c@80580400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80580400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c3: i3c@80580800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80580800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c4: i3c@80600400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80600400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c5: i3c@80600800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80600800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c6: i3c@80680400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80680400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c7: i3c@80680800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80680800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c8: i3c@80700400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80700400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c9: i3c@80700800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80700800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c10: i3c@80780400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80780400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c11: i3c@80780800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80780800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c12: i3c@80800400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80800400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c13: i3c@80800800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80800800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c14: i3c@80880400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80880400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c15: i3c@80880800 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80880800 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + i3c16: i3c@80620400 { + compatible = "cdns,i3c-master"; + clocks = <&refclk &clk_xin>; + clock-names = "pclk", "sysclk"; + interrupt-parent = <&gic500>; + interrupts = ; + i2c-scl-hz = <100000>; + i3c-scl-hz = <400000>; + reg = <0x00 0x80620400 0x00 0x400>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/axiado/ax3000_evk.dts b/arch/arm64/boot/dts/axiado/ax3000_evk.dts new file mode 100644 index 0000000000000000000000000000000000000000..0a183695e857a3a1e722ea6b7bee388bf650f0a3 --- /dev/null +++ b/arch/arm64/boot/dts/axiado/ax3000_evk.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved. + */ + +/dts-v1/; + +#include "ax3000.dtsi" + +/ { + model = "Axiado AX3000 EVK"; + compatible = "axiado,ax3000_evk", "axiado,ax3000"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "console=ttyPS3,115200 earlyprintk nr_cpus=4 earlycon"; + stdout-path = "serial3:115200"; + }; + + memory@0 { + device_type = "memory"; + /* Cortex-A53 will use following memory map */ + reg = <0x00000000 0x3D000000 0x00000000 0x23000000>, + <0x00000004 0x00000000 0x00000000 0x80000000>; + }; +}; + +/* GPIO bank 0 - 7 */ +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&gpio7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +};