Message ID | 87o7yvkcoe.wl-kuninori.morimoto.gx@renesas.com |
---|---|
State | Superseded |
Headers | show |
Series | None | expand |
Hi Morimoto-san, On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote: > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > This patch adds missing HSCIF3_A > > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Thanks for your patch! > --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c > +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c > @@ -289,11 +289,11 @@ > > /* SR1 */ > /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ > -#define IP0SR1_3_0 FM(MSIOF1_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > -#define IP0SR1_7_4 FM(MSIOF1_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > -#define IP0SR1_11_8 FM(MSIOF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > -#define IP0SR1_15_12 FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > -#define IP0SR1_19_16 FM(MSIOF1_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > +#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > +#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) HCTS3_N_A > +#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) HRTS3_N_A > +#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > +#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > #define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > #define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) > @@ -824,10 +824,20 @@ static const u16 pinmux_data[] = { > > /* IP0SR1 */ > PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), > + PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A), > + > PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), > + PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_A_N), HCTS3_N_A > + > PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), > + PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_A_N), HRTS3_N_A > + > PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), > + PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A), > + > PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), > + PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A), > + > PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), > PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), > PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), > @@ -1590,6 +1600,29 @@ static const unsigned int hscif3_ctrl_mux[] = { > HRTS3_N_MARK, HCTS3_N_MARK, > }; > > +/* - HSCIF3_A ----------------------------------------------------------------- */ > +static const unsigned int hscif3_a_data_pins[] = { The "_a" suffix should be at the end of the name, i.e. "hscif3_data_a_pins" (Looks like we do have a few exception: ssi[78]*_[bc]_(data|ctrl) in pfc-r8a7790.c). > + /* HRX3, HTX3 */ > + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), > +}; > +static const unsigned int hscif3_a_data_mux[] = { hscif3_data_a_mux > + HRX3_A_MARK, HTX3_A_MARK, > +}; > +static const unsigned int hscif3_a_clk_pins[] = { hscif3_clk_a_pins > + /* HSCK3 */ > + RCAR_GP_PIN(1, 3), > +}; > +static const unsigned int hscif3_a_clk_mux[] = { hscif3_clk_a_mux > + HSCK3_A_MARK, > +}; > +static const unsigned int hscif3_a_ctrl_pins[] = { hscif3_ctrl_a_pins > + /* HRTS3#, HCTS3# */ > + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), > +}; > +static const unsigned int hscif3_a_ctrl_mux[] = { hscif3_ctrl_a_mux > + HRTS3_A_N_MARK, HCTS3_A_N_MARK, HRTS3_N_A_MARK, HCTS3_N_A_MARK > +}; > + > /* - I2C0 ------------------------------------------------------------------- */ > static const unsigned int i2c0_pins[] = { > /* SDA0, SCL0 */ > @@ -2351,6 +2384,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { > SH_PFC_PIN_GROUP(hscif3_data), > SH_PFC_PIN_GROUP(hscif3_clk), > SH_PFC_PIN_GROUP(hscif3_ctrl), > + SH_PFC_PIN_GROUP(hscif3_a_data), hscif3_data_a > + SH_PFC_PIN_GROUP(hscif3_a_clk), hscif3_clk_a > + SH_PFC_PIN_GROUP(hscif3_a_ctrl), hscif3_ctrl_a > > SH_PFC_PIN_GROUP(i2c0), > SH_PFC_PIN_GROUP(i2c1), > @@ -2555,6 +2591,12 @@ static const char * const hscif3_groups[] = { > "hscif3_ctrl", > }; > > +static const char * const hscif3_a_groups[] = { > + "hscif3_a_data", hscif3_data_a > + "hscif3_a_clk", hscif3_clk_a > + "hscif3_a_ctrl", hscif3_ctrl_a > +}; > + > static const char * const i2c0_groups[] = { > "i2c0", > }; > @@ -2765,6 +2807,7 @@ static const struct sh_pfc_function pinmux_functions[] = { > SH_PFC_FUNCTION(hscif1), > SH_PFC_FUNCTION(hscif2), > SH_PFC_FUNCTION(hscif3), > + SH_PFC_FUNCTION(hscif3_a), Please drop this. Functions don't need alternatives. > > SH_PFC_FUNCTION(i2c0), > SH_PFC_FUNCTION(i2c1), Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 4e4ccbc32dac..d84fa59a0bcc 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -289,11 +289,11 @@ /* SR1 */ /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ -#define IP0SR1_3_0 FM(MSIOF1_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_7_4 FM(MSIOF1_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_11_8 FM(MSIOF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_15_12 FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR1_19_16 FM(MSIOF1_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -824,10 +824,20 @@ static const u16 pinmux_data[] = { /* IP0SR1 */ PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A), + PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_A_N), + PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_A_N), + PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A), + PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A), + PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), @@ -1590,6 +1600,29 @@ static const unsigned int hscif3_ctrl_mux[] = { HRTS3_N_MARK, HCTS3_N_MARK, }; +/* - HSCIF3_A ----------------------------------------------------------------- */ +static const unsigned int hscif3_a_data_pins[] = { + /* HRX3, HTX3 */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), +}; +static const unsigned int hscif3_a_data_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; +static const unsigned int hscif3_a_clk_pins[] = { + /* HSCK3 */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int hscif3_a_clk_mux[] = { + HSCK3_A_MARK, +}; +static const unsigned int hscif3_a_ctrl_pins[] = { + /* HRTS3#, HCTS3# */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), +}; +static const unsigned int hscif3_a_ctrl_mux[] = { + HRTS3_A_N_MARK, HCTS3_A_N_MARK, +}; + /* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SDA0, SCL0 */ @@ -2351,6 +2384,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif3_data), SH_PFC_PIN_GROUP(hscif3_clk), SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_a_data), + SH_PFC_PIN_GROUP(hscif3_a_clk), + SH_PFC_PIN_GROUP(hscif3_a_ctrl), SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), @@ -2555,6 +2591,12 @@ static const char * const hscif3_groups[] = { "hscif3_ctrl", }; +static const char * const hscif3_a_groups[] = { + "hscif3_a_data", + "hscif3_a_clk", + "hscif3_a_ctrl", +}; + static const char * const i2c0_groups[] = { "i2c0", }; @@ -2765,6 +2807,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif3_a), SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1),