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[v2,1/2] dt-bindings: i2c: snps,designware-i2c: add bus-capacitance-pf and clk-freq-optimized

Message ID 20240927042230.277144-2-michael.wu@kneron.us
State New
Headers show
Series Compute HS HCNT and LCNT based on HW parameters | expand

Commit Message

Michael Wu Sept. 27, 2024, 4:22 a.m. UTC 
Since there are no registers controlling the hardware parameters
IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be
declared in the device tree.

bus-capacitance-pf indicates the bus capacitance in picofarad (pF). It
affects the high and low pulse width of SCL line in high speed mode. The
only legal values for this property are 100 and 400, which are used to
calculate the tHIGH and tLOW periods for high speed mode. This property
corresponds to IC_CAP_LOADING.

clk-freq-optimized indicates that the hardware input clock frequency is
reduced by reducing the internal latency. The property affects the high
period and low period of the SCL line. The property conrresponds to
IC_CLK_FREQ_OPTIMIZATION.

Signed-off-by: Michael Wu <michael.wu@kneron.us>
---
 .../bindings/i2c/snps,designware-i2c.yaml          | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 60035a787e5c..fc19e6a8b306 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -87,6 +87,20 @@  properties:
       This value is used to compute the tHIGH period.
     default: 300
 
+  bus-capacitance-pf:
+    description: |
+      This property represents the bus capacitance in picofarad (pF). It
+      affects the high and low pulse width of SCL line in high speed mode.
+      The only legal values for this property are 100 and 400, which are used
+      to calculate the tHIGH and tLOW periods for high speed mode.
+    default: 100
+
+  clk-freq-optimized:
+    description: |
+      If the hardware input clock frequency is reduced by reducing the
+      internal latency, this property must be declared in the device tree. It
+      affects the high period and low period of SCL line.
+
   dmas:
     items:
       - description: TX DMA Channel