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Thu, 30 Jan 2025 06:34:51 -0800 From: Kartik Rajput To: , , , , , , , , , , , , Subject: [PATCH v2 3/5] i2c: tegra: Add HS mode support Date: Thu, 30 Jan 2025 20:04:22 +0530 Message-ID: <20250130143424.52389-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130143424.52389-1-kkartik@nvidia.com> References: <20250130143424.52389-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB57:EE_|SA0PR12MB7092:EE_ X-MS-Office365-Filtering-Correlation-Id: a216b733-10a0-4dcb-2e34-08dd413b4ea6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|7416014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: XvmIcTkpjpp9WFb3u0iUN2Mvu+oDIH4P+oxEwVc8GBonBxPAV9KOvlzGulIj6TsWdtAbdgEk5khSwk1kTLITO7d1GVBfmOGtmSpr71Gen5wux1X+WWoySo2h/M5RoL7d6vSG2FVL+bnN/WCN2iFRsH1n3RElmESASyeTGZulOGvKZZiKMwId3cg9r5ZUu9oY2cKIOAayYprUrrDUDpwCeGStCEpwCjIZSr2MGiBDu10xf2/7+6hamN3eY4kuXl+EGoTGlVX5JsjyvkzO7TWop5otkqd8LxKolwAuf0SDq+u6PFtlgXJxz66FAyrHoHqLYFFqzjaO4I/uX3IsB/2iZqca2rdg37qwYqRUXLDTgqSyy1hPD6vkreCbuVmziwPoo5tSdxocXg6FPHvfP88OsALB2/1RBGe1W4nEaBcbU2X49folLPuDVEauIyHDjaVSHnQWrAoiKF4YaCf76/wuIkluNETCVAPDa8VgFU6C1SHeUMcxdvj81RO1owyA5WUyew3S8ZyyUeSJk/FHdgLbs8AoCiIjPhyzAuv25pmLS6v+Iw5scA6KCB8Y2UoR4/+TTlMw7JKTgPsR+Ke0CwqvJh3vYp2y5LE5fvWptZNGTE/B5AYK8evpKpI/u0mdYGvQbQ19H4YTCt2D9tcCNLJb8UWQ8fmGIQ/cscn0m9J+TefK+073IGSLaLQ+FDXeZSGZl3ySr+l38DL5ZtDicL2CV7ixuOYUa4OeAJMstMBy4l2/rs/Lca6Q+UbDTVNSaxQCJyf7S85SP3Zt1PNQplm26sJpnRJKQBeEewli2o0z7HJFwY6osuB5cpmOecdtmZ+F2vjvbR4yEK+T46DRdkAWhXd3impDA4C/4RbQQ9eMzUkHKVklL/M2CB1NTp5Nf6sHSEDPiC2QO6YMsA8t+6vuSWz058Yz4EZDJ7GWeiOwUIykgAAC8liPkBSdl9jmA2c6g3B0qPm7qJ31DXgwbNVowxZIxIWbITygumo5tTPpzk4A3MhRkSHeOzSLGEpkJloIZY0f61gb6zc7+bo+QJZENH6ZaXp6pKADhtNJY8YmT4ozhAqVtq/OrAplbes7I/YfLR97W/d05UtxWICmG0vUdi6XYM/nkaxWFbQv9vRAO/wTVNAEZOcfLtv438H2SvC+MIkt+cTijeRAbKDFmC8O8RHy1o3jNnyMK4tXtHCOTqsEudbgs4eeLKhwVCaTp6cfD0tfCLdg2nU6iHwg20ciR0i11wQ+lqT+IN6/nfHR7yPUJw6W9j2ijEAaLrqf5MsEUOfVMPLkSWQd9+/vHeT3fXSc3Gr0EY2k7zxpGvHa5fYOO2ba3lupxD1oWomDJximhdADV4ypaq265D3fH9Y6bd33d+Px2zllMSaErM0rgjqnW7px9nq5vMWqp54+0f9Ex78R+oiea1gfbyHxYv4VLLNu6nOcVCI+ARxafHPmJ5uVVaZg6xtYdF3OD3VpAMYprK3wVuymZe8xUuU91ki+KkxFphmj3zyFBllhe6+FnsYs7B3SxmUJ5cwaLpNgpzQZ X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:13.2836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a216b733-10a0-4dcb-2e34-08dd413b4ea6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7092 From: Akhil R Add support for HS (High Speed) mode transfers, which is supported by Tegra194 onwards. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v1 -> v2: * Document has_hs_mode_support. * Add a check to set the frequency to fastmode+ if the device does not support HS mode but the requested frequency is more than fastmode+. --- drivers/i2c/busses/i2c-tegra.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index b0dd129714a2..7c8b76406e2e 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -201,6 +202,7 @@ enum msg_end_type { * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the tuned * timing settings. + * @has_hs_mode_support: Has support for high speed (HS) mode transfers. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -220,10 +222,13 @@ struct tegra_i2c_hw_feature { u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; u32 thigh_fast_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; /** @@ -684,6 +689,20 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow = i2c_dev->hw->tlow_hs_mode; + thigh = i2c_dev->hw->thigh_hs_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode; + + val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } else if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { + t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; + } + clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); err = clk_set_rate(i2c_dev->div_clk, @@ -1181,6 +1200,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |= I2C_HEADER_READ; + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |= I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ = packet_header; else @@ -1621,10 +1643,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .thigh_std_mode = 0x7, .tlow_fast_fastplus_mode = 0x2, .thigh_fast_fastplus_mode = 0x2, + .tlow_hs_mode = 0x8, + .thigh_hs_mode = 0x3, .setup_hold_time_std_mode = 0x08080808, .setup_hold_time_fast_fast_plus_mode = 0x02020202, .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, + .has_hs_mode_support = true, }; static const struct of_device_id tegra_i2c_of_match[] = {