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Mon, 9 Jun 2025 02:34:34 -0700 From: Kartik Rajput To: , , , , , , , , , , , , Subject: [PATCH v3 3/5] i2c: tegra: Add HS mode support Date: Mon, 9 Jun 2025 15:04:18 +0530 Message-ID: <20250609093420.3050641-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609093420.3050641-1-kkartik@nvidia.com> References: <20250609093420.3050641-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6732:EE_|IA1PR12MB9029:EE_ X-MS-Office365-Filtering-Correlation-Id: 19b77032-a342-4b71-2d1b-08dda738e0b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|7416014|376014|921020; X-Microsoft-Antispam-Message-Info: oI4fhRgbEgOxyGb+mvXIIeEmLsW5ZUo0Cs8Skh4hZQxLR6YyKYzkx5Uq54U9AZvLyiixcmsONwZEOEdwHKs6pQFSVfUH1oYTAQvJzQtXC9yncdr/RfkZqtFudhaQjUPb2l4kDHnm62c/f5dXwP9aba1/wIYB16pVyRgc7OpfUjrbnUCTwK1Bb0N9QGHWf3UTukmUT3LJv4VQihnpGz+z+UrOlIpQdWxoyI+Mjt4zw/WTzKKSrThx84KjKX3zYzWnz01g5cgztE33u+wKdaXam6kIyByrMoQfFVg9TF9RFfIXe7CmpzbGdxXJuMVPI6r9tzI6eFbRmBSGPI4hf1cfEmnPCmNX7aHPnDT6SVxauSnJvvQhpze7IyqdBzqBYVJC69bQ31zPKWgT3F3LzNyaTiL/1OaKmDylcJrmCZ+C89PFVAUr/ZNpmOihpDIKAx/a1Hs2mVILtUrgv1cYCsWGLX8LbpEB6FCQePKsZDVE8Kb62QhR5rvZaieuGk3YZaluOYCdY7BZB6qRYvJIzynRjb0xbvhaVB++FkF0CJXwcE0hN1wmTSudAU3L8wdhl0EoyyL9LB75mwU3tTCdkxpIJ2llIcZAalLMBUQSFYqMk3A7QkZsdc5VkejrXUpuDIQ/tV77G8QoCiCm0aXi/JU5Oh7FkH3i/y0g/3ZiXhO+agGW9qEZG+pSg7ciK1+PXvgp6VqFhBTpgaBYS7OLzBffNLi2+tlqDLp5yNZHcQ/YaWQOTsRNREAq6lWcAWVCnQ81fKLgqU/I6asLxdtKCnx3Mc7MNaFnBZfc6YbCDIENeA6YB4NbR42ldyG4SYgOj4M83gha74U1bSnZADSNYyjRNFFylCobv+iRKwzxdnBp/uJ+82bRhK8G5gFdJqxYMWP3nY9wMZjD7vyV/qPlTxIgj9GFQ68Lh0WPyGc2VW7ESRimJ/+Njtvzq0bFGiofjtvzfxFXSHEz45rXyFbGmw+yG4Y3E/VbopRhxyQDNT2EOF07jX6J0D+/+hZTdUGqn0iOHhlV6AbVpZhlpkFlduNguHyrpfbEO9udlEsQfDODWAjNWCaaLj+2ty1X3X42rj0TpfHxMN7W73oSKyWak+BSF1n4+02g86ieO/hFNsJl8YKkcP5QuUdKw115lotcJ4nYhIXgJ06U/ijrZMuLmEmUieUZEI4wbV62kEs122SP3I7S79JBdfVTB/yR1tzElSacX5YSqE66fHMj4/rhf2pVuH5jirHFV5xGAL8BzjBj0N4APDC4bZcx+aIK7UiHbFwnXG5t4ggCwDP+iynDBv6gPSD8cyM9x+1KxYA9YzrpND8JHaDyCdYH0NutC3OPU4ELXmbW+6w8NQFNk1+gsmciVPUNJQxwcgW7FwIYfUdEWPUK8cKxXLnFqyEAYXVosCelHkv6ophAYUx0Hg624rIkbCLGk1EQy7iTFnq8Hk6lnRjyYJ2eh815VI0eLuvS6fs04dkLQA9MXJT1Nfb5cGTKkX/L9nnm1140Ztej1jWA+Ez5+ij/djeTvRA2CIJ8H40QKIn/S/xwWqRy7De8X3gPZA== X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2025 09:34:48.5795 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19b77032-a342-4b71-2d1b-08dda738e0b5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9029 Add support for HS (High Speed) mode transfers, which is supported by Tegra194 onwards. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v2 -> v3: * Document tlow_hs_mode and thigh_hs_mode. v1 -> v2: * Document has_hs_mode_support. * Add a check to set the frequency to fastmode+ if the device does not support HS mode but the requested frequency is more than fastmode+. --- drivers/i2c/busses/i2c-tegra.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c7237d26b813..d0b6aa013c96 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -198,6 +199,8 @@ enum msg_end_type { * @thigh_std_mode: High period of the clock in standard mode. * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. + * @tlow_hs_mode: Low period of the clock in HS mode. + * @thigh_hs_mode: High period of the clock in HS mode. * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions * in standard mode. * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop @@ -206,6 +209,7 @@ enum msg_end_type { * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the tuned * timing settings. + * @has_hs_mode_support: Has support for high speed (HS) mode transfers. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -226,10 +230,13 @@ struct tegra_i2c_hw_feature { u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; u32 thigh_fast_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; /** @@ -706,6 +713,20 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow = i2c_dev->hw->tlow_hs_mode; + thigh = i2c_dev->hw->thigh_hs_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode; + + val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } else if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { + t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; + } + clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); err = clk_set_rate(i2c_dev->div_clk, @@ -1203,6 +1224,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |= I2C_HEADER_READ; + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |= I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ = packet_header; else @@ -1637,10 +1661,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .thigh_std_mode = 0x7, .tlow_fast_fastplus_mode = 0x2, .thigh_fast_fastplus_mode = 0x2, + .tlow_hs_mode = 0x8, + .thigh_hs_mode = 0x3, .setup_hold_time_std_mode = 0x08080808, .setup_hold_time_fast_fast_plus_mode = 0x02020202, .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, + .has_hs_mode_support = true, }; static const struct of_device_id tegra_i2c_of_match[] = {