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Tsirkin" , Nicolin Chen , Niklas Schnelle , Shameerali Kolothum Thodi , Yi Liu , Keqian Zhu Subject: [PATCH v3 01/15] iommu: Add IOMMU_CAP_ENFORCE_CACHE_COHERENCY Date: Tue, 25 Oct 2022 15:12:10 -0300 Message-Id: <1-v3-402a7d6459de+24b-iommufd_jgg@nvidia.com> In-Reply-To: <0-v3-402a7d6459de+24b-iommufd_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR08CA0007.namprd08.prod.outlook.com (2603:10b6:208:239::12) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|BL0PR12MB5506:EE_ X-MS-Office365-Filtering-Correlation-Id: 72ca51c3-1d1e-4198-de07-08dab6b47902 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4pbUp6c2B7fnE+qu3KmyVrY/NByFvCte0lc4w5gDxHFKM2oGb3fLEQIfJYKwNTJD/d1neph4HKLPAr4EF3amEF0Q8EejYIatn3rwm59PgYkMpRZP1+yYNHjbn7nwnoTyCp4r1gW1A8cZsHr+sF3e+jE5MJuTnhgdT/Kt16RvT2Ot+Afk/ebSrEkmEBRHPGSrjqsCHdVqzPCE/g9grMQIgrpJOy+P+49JHorOA/N553sATz6voElucu3JO5oCEFVRv/pKIWPSQkz3nCKq1jNAyM4huP1MsmK7z8Yh4UhFF7ZjgDl+q6nw7cHKyhX4WwCfk/qEE6Dr1Ga2zcNQ4q7UCelg0HOmu9Zy82lT0g/7U31FiA5r+3gQbOP+wwpTVY8rDySTFgOG+yY/rqUUT/R1KDUJhFabTKnncuDyIU07isAICh0/oaG1RkYzy5bzGWz/1oYP/Uakc/Q2IA0hAYwDtx3MYUNEH9S4rIdaeB34p9HmNWNpNaL34K5C75jQcI+A7tH+btbMapTyzDuMkK57pKAcEIyaD89GLExf8N9hM3h8OSvsi0xKf5G05Qp3Y/L77ssMrTfwJP7+pOkC1Aajkk0h10zAxzbL4r52ctfnuHcQYAwQGtLGSoNbcVg1sQM0Z+CgzbAuqy3/+6Em9KdlE/WkEWHML+M1CCmVRnTja3mtnfgYBZWjU2gGdfeZlMvQQSt/SAKetua6BpVPNg3TkR8VYEHAEMK96AMyjSq5KMfbA5qHWhnbhD8NdMEj5+oKawsT8rGgP2gmN5gmb5JxRg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(39860400002)(396003)(376002)(366004)(451199015)(7406005)(7416002)(41300700001)(5660300002)(8936002)(66476007)(6506007)(110136005)(66946007)(36756003)(4326008)(8676002)(6512007)(66556008)(6666004)(316002)(26005)(2616005)(921005)(38100700002)(186003)(2906002)(54906003)(86362001)(6486002)(478600001)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HfVHhgbRWCAkLsHxNpjHJy2lIXeYWeIyknVuM+FXMT/ZrpNfsz8nKvwnGTfY59P0K/ogRHoPGNHMSioUE0sexzG4WNd0P3gMsCrQDP5MSPC37XjqYiv74N6DCqaDKaUPzdq/Oyoe8xzQ5BgTzFuxGSjgEPMwXob99HgjnZY71WqP7kipl8s3CEL+uS3UVepmuhkjEU4SYx3FWT2+medCfe6G1NoViU6aufM1AnINvtBZsDAhHu+4mK7A7eDvDLFsl3WMj1/L4AIJZshuDgXRVK9shppakktytY8aSJkrTv9f7iU1B0OhcVuo6PoDadcBs/RXkSW6W1/5AF/qhrYnTSAu0QjZZF7t39WB9Kaeb5S69cQSGHoHm6NLuZ82kPTZJrYJUAPoyoTkFBHDwpnHD7SmyrNJLqS3wZxSODfO1QlUTUdMgSr0asNdGApvO7NAHgRPnNkjvD28lBCyyGG2GKD/Y+F+iHme+qSbqOJ5FZMPQUt10QnIm/pp4q5+3I7WTZyo1+bqdeON0YbAXyBMtAwj1CcwSNkuoUWBg/eU4wBLVjA9E1ATlN42gwREoNZK825PVUDGkA3hs7ulG/5WYNOXwRjWJd2EOqQ0+E5oqtynnrfjqLTeuFeUnrUC2xjPzAWaPMoKWhAJD5qrTfnsJsUo4uZRFHSg7YoAEyTdawaPXJx3bUwoyHgPC1lKczQxI+LeCdnbLc3ATN55ulv20beISSVsHnIF9YbJFQwfkzH14CbGHe4fS94POqgS4watWGL7wt0ujoJ9Mh+ZanAOBB2uRVK8Jy1OxXZ0Q2QyfYtT2XZy2qVbpnK5AFEqqoxRy13IcKsR9DIe7QXIki1+AI5KqVnfkxJHIruyaKto01wR23LwPMqBX5f5kIdk6uwE68hA7hPNVkRvd4NFRxiKHibDr6JOFELXQFz9I1TgNvDnILjc9SZJDg+utW17J0hQipUECqGfqbEVtxfBxEHTMJNUvqANms1IkCTXKOZ1v6YW0erKqYkOBxvDyH6pG7EcPPVj8X9kNZkgWobVLArBig3+yAmaEyWeJcQyA9MIlekU+SJUQb6InHWhhC42jZeFAyieXdnfNuJgqYB0jNzhR2TD4QV6PlZc5IFoCeDr01WqojZl85Guh+cOSv/GHSTuCsVFjdN+JP0s91huBt44TZVMM/criAdH9kW6LOvQGKceLR7hdMhmypUyEkMSwfIIu1qsz3FEUnTIvEnVv7VX4bCVi6T8KZFJZeL5tk7h/ptlLmaGk85X07i5sl9ULbkFT+9buUWbQOUdE4q8XuN6NlMcNN73pWvKNFAcRwM88DXLD5J1SExb5lKsAf+L5wnk99IiGXOevFUqH1WNDG76+u4d9yDZMwgWGasz6L4VEq99CjCrVuIXdlTV2aKc7j0Q6PQs9r4RwqYpOQSM/Dn/8xnatreWSmtEKKiiX8/27D+VufyHvA7EIuLt9p506dW3A68jv84HHOv1iptDcqDcBOMz3Q4qmKqL7tgKpt9Hmj3MBVLA8PrMZj6yQDf2juIWBzma2FfGJOCjzojp1rywqU8zlblVgzvgLZudyCT8rII= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72ca51c3-1d1e-4198-de07-08dab6b47902 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 18:12:26.7727 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XvlH+ae1//R+qJQLwSkSE+lxvxPEV5qEgMdIuGtQQQ9JqUSZG91q1FVYlo2RDU2x X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5506 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org This queries if a domain linked to a device should expect to support enforce_cache_coherency() so iommufd can negotiate the rules for when a domain should be shared or not. For iommufd a device that declares IOMMU_CAP_ENFORCE_CACHE_COHERENCY will not be attached to a domain that does not support it. Signed-off-by: Jason Gunthorpe Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian , with one nit --- drivers/iommu/amd/iommu.c | 2 ++ drivers/iommu/intel/iommu.c | 4 ++++ include/linux/iommu.h | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index d3b39d0416fa32..d0802cab2a2f0c 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2286,6 +2286,8 @@ static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap) return false; case IOMMU_CAP_PRE_BOOT_PROTECTION: return amdr_ivrs_remap_support; + case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: + return true; default: break; } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 48cdcd0a5cf346..438ba997fa230e 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4458,7 +4458,11 @@ static bool intel_iommu_capable(struct device *dev, enum iommu_cap cap) return irq_remapping_enabled == 1; if (cap == IOMMU_CAP_PRE_BOOT_PROTECTION) return dmar_platform_optin(); + if (cap == IOMMU_CAP_ENFORCE_CACHE_COHERENCY) { + struct device_domain_info *info = dev_iommu_priv_get(dev); + return ecap_sc_support(info->iommu->ecap); + } return false; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 3c9da1f8979e3a..40cf2d8393465f 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -108,6 +108,11 @@ enum iommu_cap { IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for DMA protection and we should too */ + /* + * Per-device flag indicating if enforce_cache_coherency() will work on + * this device. + */ + IOMMU_CAP_ENFORCE_CACHE_COHERENCY, }; /* These are the possible reserved region types */