From patchwork Wed Jun 4 17:15:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 894116 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCDDC20E000 for ; Wed, 4 Jun 2025 17:16:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749057395; cv=none; b=ZKF4VwOIdYvPvMGsVexGa0pz6kv4UhlmuSMr7H3jo5IidL4lkzD/tJ7zBULLhDKmcYSnPu1Ets2gVE6EHUDOEWvknwaVIvlqk416INtWQTBy2CdOqWXBTXQO9rIMQZeRZzmksB9qkxWh5/2Q+nJ9vdGyNPgqpvzTxWObbHRH4mM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749057395; c=relaxed/simple; bh=eDl9/FLAtbK/flEu4IAVWy5gxeoiMiEB2MqW8GUlkO0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Wz/Sa/LXdXN8gELot6WkJHAiHOOExwg0RIWPJDCy39lTVi3o3k42UEVlJRyu0bOBUnfcXPJBPP+Yq2ohooLGOaytb3Leysk7BjxuHG9IcuRkTEXbMzDnLJWIBF79fjycTQxaIsUm8NsRThlU/1hZVhzqXHjl7/7aaPsUJYEzRfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=yoaeGjxP; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="yoaeGjxP" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-309fac646adso1218078a91.1 for ; Wed, 04 Jun 2025 10:16:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1749057393; x=1749662193; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OtKPI2Naweua6KOKoYxAPpZu6IW/4+X8POy/Zey8NJ8=; b=yoaeGjxPr4luUH/txgoTW7mY5bV7ZGZQLs9Xk7ef7+Vt7fZvO4YAwksAoySxzKzhuC tGlx10uInh5DARdGQyXUVPWZGHMBmaHig7rGwbTB0m5v5vRtjYHiy9Tp8lbRJiq+6i/T wnBExoJUAG5j2mP4qVvh2Rkv6rMwBBy5d/6L8Kz4rtyMNHMfxZ+CLTcUCUBFrhVHbl+m ESnHL48xAmACxxPIg2v8jKE2/WgL55zXrCbGb6xVjs753ohXgP+zvJVIZ3aqxBnYohMG 2H2W9v8QJQVfnch6QkUgnsjQl41AK59dc5Vp8HVhuJ4xL7/4NkRwCUO4CZYwOuvltagY DvNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749057393; x=1749662193; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OtKPI2Naweua6KOKoYxAPpZu6IW/4+X8POy/Zey8NJ8=; b=JzcXrkXU0BD9XMpZRq/+w5Tb/cXnIKvjwiXT6IRxF06CUboHgDh0i/oRx82i+GP1T0 ZRvJ3ciwoeUJsYW2OBiqWIYPIJ8KEbvrPHt/RPO4g3mHQNkS2s+YmrxBFxSwkeUwMV2U A26l/fN7i9g97Gqo93d9T48v8DYPTabk5huzgl4oqGmK88H5PQ/+NYvX21+2M1LP01ty FuEnXfWT9YZ8W3/2OCsHrbr+dSw3+xLEgbaG+yNq/eE/fYLuLBFdKRveHHjJWLqAkBWV QAydStbGK7ym/6LodeBJEZPJIS7rfQKJZdDJ2Q+2Ngum/dfVmjJIHrhl0A8jHOBHshwO yThw== X-Forwarded-Encrypted: i=1; AJvYcCW9LiEC2jB8arZRkIVYex4zIe0dLgAgqXrkLB4/vq+RqeIejBEqVbsGvDCKwSUYBLEto54xIKFHiSFIcfw1B1M=@vger.kernel.org X-Gm-Message-State: AOJu0YwDlhnDX9tPWF4hkZlTW6WY23JNZv3fg9Mf1aTZCLo047/8CDQ3 xzpxVAEtVEmIgfKFnuekdTJ0kL4VRe+PTvy5MLfBCtT6HysS75dcf6qoI0cIvziyZiSqxycxZfh WLDWl X-Gm-Gg: ASbGncsTrtwQBK2gfmddirYA/eEv/xFQxLDMVwP5Z5mLC3BLk7OKaqRlmO9rRigR7VF 7mDLS41wCCcadCvNkkCqtcQdLTWNmyoPaoh7VndT7qff+Ju36XWHY3SpKDqKrCxkRbsjIpSfw72 xqpV/xPt4peaUAKQMUDXa/tUCejVKIz2JNqG1K/az58wt4J3lty7o2xQnifKuinOaeEZXv/Edr+ nkPIHlkvtodthxvI1lRaTt1siG0eftwbGUGtTEUDldUEga+ugRoAB78Ha1ZvWiT6af7xz3aNLHC dxttsV+CCLE3nj8Em/5w3u4ZvywrmUtIdeAUd3LDp1xAk9ONagCf7il/+eoRRQ== X-Google-Smtp-Source: AGHT+IHE2S1H2Kp8xKCw0ZpGRZuaXR3xr247uSwdF5+LhUIbu38f5b5b/U4ShdbPQxItyXeG4sG0mQ== X-Received: by 2002:a17:90b:38c9:b0:311:b5ac:6f7d with SMTP id 98e67ed59e1d1-31328f8b1admr363794a91.6.1749057391469; Wed, 04 Jun 2025 10:16:31 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3124e2e9c9fsm9178972a91.30.2025.06.04.10.16.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 10:16:31 -0700 (PDT) From: Deepak Gupta Date: Wed, 04 Jun 2025 10:15:30 -0700 Subject: [PATCH v17 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250604-v5_user_cfi_series-v17-6-4565c2cf869f@rivosinc.com> References: <20250604-v5_user_cfi_series-v17-0-4565c2cf869f@rivosinc.com> In-Reply-To: <20250604-v5_user_cfi_series-v17-0-4565c2cf869f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 `arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ | VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is updated to convert all incoming PROT_WRITE to (PROT_WRITE | PROT_READ). This is to make sure that any existing apps using PROT_WRITE still work. Earlier `protection_map[VM_WRITE]` used to pick read-write PTE encodings. Now `protection_map[VM_WRITE]` will always pick PAGE_SHADOWSTACK PTE encodings for shadow stack. Above changes ensure that existing apps continue to work because underneath kernel will be picking `protection_map[VM_WRITE|VM_READ]` PTE encodings. Reviewed-by: Zong Li Reviewed-by: Alexandre Ghiti Signed-off-by: Arnd Bergmann Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/mman.h | 26 ++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/sys_riscv.c | 10 ++++++++++ arch/riscv/mm/init.c | 2 +- 4 files changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/mman.h b/arch/riscv/include/asm/mman.h new file mode 100644 index 000000000000..0ad1d19832eb --- /dev/null +++ b/arch/riscv/include/asm/mman.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MMAN_H__ +#define __ASM_MMAN_H__ + +#include +#include +#include +#include + +static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot, + unsigned long pkey __always_unused) +{ + unsigned long ret = 0; + + /* + * If PROT_WRITE was specified, force it to VM_READ | VM_WRITE. + * Only VM_WRITE means shadow stack. + */ + if (prot & PROT_WRITE) + ret = (VM_READ | VM_WRITE); + return ret; +} + +#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey) + +#endif /* ! __ASM_MMAN_H__ */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 428e48e5f57d..dba257cc4e2d 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -182,6 +182,7 @@ extern struct pt_alloc_ops pt_ops __meminitdata; #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ _PAGE_EXEC | _PAGE_WRITE) +#define PAGE_SHADOWSTACK __pgprot(_PAGE_BASE | _PAGE_WRITE) #define PAGE_COPY PAGE_READ #define PAGE_COPY_EXEC PAGE_READ_EXEC diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index d77afe05578f..43a448bf254b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -7,6 +7,7 @@ #include #include +#include static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, @@ -16,6 +17,15 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long len, if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) return -EINVAL; + /* + * If PROT_WRITE is specified then extend that to PROT_READ + * protection_map[VM_WRITE] is now going to select shadow stack encodings. + * So specifying PROT_WRITE actually should select protection_map [VM_WRITE | VM_READ] + * If user wants to create shadow stack then they should use `map_shadow_stack` syscall. + */ + if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) + prot |= PROT_READ; + return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> (PAGE_SHIFT - page_shift_offset)); } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index ab475ec6ca42..78b27164bf83 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -375,7 +375,7 @@ pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); static const pgprot_t protection_map[16] = { [VM_NONE] = PAGE_NONE, [VM_READ] = PAGE_READ, - [VM_WRITE] = PAGE_COPY, + [VM_WRITE] = PAGE_SHADOWSTACK, [VM_WRITE | VM_READ] = PAGE_COPY, [VM_EXEC] = PAGE_EXEC, [VM_EXEC | VM_READ] = PAGE_READ_EXEC,