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Sat, 14 Jun 2025 00:15:45 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 25/25] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Date: Sat, 14 Jun 2025 00:14:50 -0700 Message-ID: <35c3f8f83d6bf5544d3982619ff1d7919b67fc07.1749884998.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0F9:EE_|MW6PR12MB9018:EE_ X-MS-Office365-Filtering-Correlation-Id: e10c548c-a8df-40bf-4edb-08ddab135026 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: AR9/hexqZ+bAQdMiEUeFDcILiecVX3DO/EJLZn9EcuCH0OSjeIprXOH+sXL70gtXVTET+Z8gzr2bvxIGADpx79++GvSqeKDymxHQi/EBoFne0mE+H3so0Q0DsT7Nqs+XPVXfC7Ic6kAYc4KweQZGoo2gqB8/WsrJtbQSalCWxJDDwuievCd5O7DcpdBsjtVazgJbd6LFcVnhWO7U2QNHXCH0tLs8Q7ybu5aP7OHJkJ5/Ca6lrjsvkbzgVCXwOQN8R55wj2JoUCU3s9AFhD0n174/8oL3YLK6xgI8f3caSW0YgXs1yoKgc19gd+934Gvao1LROFU8Bub8QETUdzcJZFsGbg+7EapNjBZVTSwSSbmWcwyCJa3Q0o6ZL6yCJmeJBMQRg1kgE5JYFwvNFszcP21QBzhKkjIaaniAynKS/3mv8vmGdgpLOip1pUmv65QRWYyeyUTvKC9+zBQ4DggxB2KsZzMpKUXG/ZZ8BxVRLoJfSl7Rnreaxit9RhK3NpSL+FI8gCxPDjieidUPpnyg6lNN9ltub582Ijg/e8IiTvaEYBPNPNoMLVR0QPzXBbBKXc+2NZMoZnL982gSQPGGsdEPS1dZfRctebUKGAk+bFI46QICDcXRcih88IQTHDL2CG2wYuAHkz84iC/WnFmAphLvbSumqRiSuPYQZBRDxx7G4E9UFJ2Q7nEbmiRTy4+k1gTNwcPlr6YRFOas3zwdJbvz8XP9KJfd440K2jebGpnu4yGgnFEZZgf+6/boZlsPyeSJB+HP7YMKSHSqcwRaEBj64ZwPVC9CS+IiTbCTBXPjOXD/zref2SgMBCGGaKQ4l7C0g6MPHUI0i87y3u4vrnpio+bF1q1cNZ7ytPrS+JchyYFD1O8v7UcS+clQHBgaMzmvN7o0CVvjAIEMe9HWfeREC5ia0CrXAcwJyWZShaX2iY8pYOcQ7e2f6dXhE+jaCPO0Rt7O4bI3g7rGyHewhKdWbGcYkLa+Me26IJHp5JZKxAQYE1WxM+i+b9oe5rZ3MSP7f9S4qke9Nmm8QBIOQTZjGnXeif662xXj6WLkWgVAoro3hySOMtEPpcWQE2sF9VwyCn/lOHAZBCLcz5iRKyCRI14P6w4xZQmLLgLjme/UQ4Eec8w2kZ8ypYqRROL7k3CzTUGPck+FerLpT2WP0DjkxragdnhX8T2S1Ksbaq7VzoEJ4J07qCBPrzXojIXckxfkz0BvQ2lTzSrQgMElE0bI8C6/c7VgTV7/mkUeXJ3n9HUwFG044L6bVjO3N0xTcNkR2g1M+zV5HqMkGoiL0L03UqUQ4CsxORakygWD39tZ9LN45pHnxX0LDBfzHJVbWSv4xTzSC30uNvWibg+uW1EDR5NDF0JnocbLv0tC4kKlatkIsATndQP0erx1oLWtujCk7e/oUpGdRpXVvZnWCuVKLezQGF4Dp2JH3Q9wzoeRkd2cVmXc0OWxrSA9UgcpLLAjUNcm+wB3/+C4kJTa5n70AtGZ9GmhtKs9i1gztTYRQ9//sG8n2oLFX5O8Ww9X X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2025 07:15:59.1833 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e10c548c-a8df-40bf-4edb-08ddab135026 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0F9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB9018 Add a new vEVENTQ type for VINTFs that are assigned to the user space. Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. Reviewed-by: Alok Tiwari Reviewed-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/uapi/linux/iommufd.h | 15 +++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 1c9e486113e3..a2840beefa8c 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1145,10 +1145,12 @@ struct iommufd_vevent_header { * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, }; /** @@ -1172,6 +1174,19 @@ struct iommu_vevent_arm_smmuv3 { __aligned_le64 evt[4]; }; +/** + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) + * + * The 128-bit register value from HW exclusively reflect the error bits for a + * Virtual Interface represented by a vIOMMU object. Read and report directly. + */ +struct iommu_vevent_tegra241_cmdqv { + __aligned_le64 lvcmdq_err_map[2]; +}; + /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_veventq_alloc) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index ab9c80b4f2e8..c231bdcd5d31 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -294,6 +294,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) /* ISR Functions */ +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) +{ + struct iommufd_viommu *viommu = &vintf->vsmmu.core; + struct iommu_vevent_tegra241_cmdqv vevent_data; + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) + vevent_data.lvcmdq_err_map[i] = + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + &vevent_data, sizeof(vevent_data)); +} + static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) { int i; @@ -339,6 +353,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) vintf_map &= ~BIT_ULL(0); } + /* Handle other user VINTFs and their LVCMDQs */ + while (vintf_map) { + unsigned long idx = __ffs64(vintf_map); + + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); + vintf_map &= ~BIT_ULL(idx); + } + return IRQ_HANDLED; }