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Sat, 14 Jun 2025 00:15:32 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 19/25] iommu/arm-smmu-v3-iommufd: Add vsmmu_size/type and vsmmu_init impl ops Date: Sat, 14 Jun 2025 00:14:44 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FD:EE_|PH7PR12MB9066:EE_ X-MS-Office365-Filtering-Correlation-Id: a162a9dd-5e1c-4e94-c7ec-08ddab13497f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: tMWtcaoWvvT72LEocU0ay8+WFoqSq6bSFEYSFhobtWpQ5dZOr3joNier8f8on9ozVc1EGRXVddJOhTy1GfseL6USagmEeekytKq3I/RbcyUtLCHW7QgyOTa6DTk5Ve1CCexKSkL3zDFyO7GV61uu/faoWZq7qJ23HNMor/hd5H8D4FjCum99VGy0ogMSsi1qhjZeFygaf4gRaZRVg6ClbbXEoWsgCFoFY6FD58PjpkfhE9yl/bQDrkozw6C+nImd2B2GKpcBiG4RbyVEacqEjy3l1fa5uuGYiliQ27LeAo7z9gP5GMcrMvMU+Yr7XmA12/FWetDTN3q7+xmi0dC342/LCElJadZQ8i0C8OuVze/wGlEX4/wUDhdAiD78TRTDkVRPZXiAZX5+TsQgV3RS4YyUZ9l3R60QJZy9UxfmWuSgO3/v27qxblvcMY9dcaNMeTy7GGSyaa8MkVBC9KH3oh6wF/FBod5Z6RYwkffJuTzr1l8zynRcGhTCzZf94+eAnsgShLLlVk0y6mSTDqmqEJvHd/WDMOd1mBZ4/zrfYxgkYlsjM4z1TTWgMfqurZo6dT8sVqFz+v5TPcqSSuRY1eDx5cDuR7tRNxScVty4m/0aTWXea/P58R1ODEcf7ApcyG2uj16A/2SggXRDKP77NFMu5YkwOt04UtEH8xl9U2f8RsXD6wNHvgkpsdhRqDWTvB3HN62ITMXV/2sWy1RRSKuA9B6prTZWqRNOe4v/e4Feyje9cwJ0xlTOln8OmQ0lDI0Nk19dqOzRGM1FnixkI8ACbe6wmzHa6KieERu/bNDSXdo/xxOgivprbKu0ebLvKFy4g9FNeKXiCHoUOxOqN4kpFVu40ScdvxFf6/nUvHfgZeMQHIfsUFjAQPTPoeBV+iLBRDS2x2WQC+7aBxrRW1Npv2ojreMlQM9iSfDlXWlpaWOEj7LtTGSo5xpIb/yEb+0wEe0INjBIGu7uFLabAPwkVU9Y3kDRaJ3+q41ZkQuPMX6eLX2qjLmOx5uIV2KKVr4nJDw3Ibag+xoQ7/BpovNZsHMHDnFQ1h2YkhTdLW2QMXTXEddv57Uf3Cq/DOMyewJWTI9cpstK34KsjDnyRjFAaA+T+z8yUsx4Y+ZZfY7IiT/vSKXPqIJkIQRTYquZSPSZ1U3NNem6aJzUqJTIAEhc75kQqby2cmD0VYXWuhByuQGfwbZmfiW8HFeODe+UoMj4P/kFgqBzsy8RiF+GD66rnimA0FO3trusTJkKHXESv0JTX+HzT4Qx0TMhEQvhDeXy27Ctrnq9IXFppqzrjx5yar4/rSv/WrcLRYJ5ggGho6RsZVUn01ECqYjxMkGxiiUn8gfQMZqp0iMLrGpX8XKnGe9P+0Mlito4cF8R14thXe6j/j/FGheRcelquTYnUQcCf2ORYnYVNxXBKwmi7EtucVyRcwyOGv2JUYF72cvvIRLfsAHEF6V3WyrC6jW8QMu7i1SoivSEGKhRVDgnjLeTg6qzGtmNEM2XAHGuCQrJ9C55ywHshia9UYTYXeMT X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2025 07:15:48.0355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a162a9dd-5e1c-4e94-c7ec-08ddab13497f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9066 An impl driver might want to allocate its own type of vIOMMU object or the standard IOMMU_VIOMMU_TYPE_ARM_SMMUV3 by setting up its own SW/HW bits, as the tegra241-cmdqv driver will add IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV. Add vsmmu_size/type and vsmmu_init to struct arm_smmu_impl_ops. Prioritize them in arm_smmu_get_viommu_size() and arm_vsmmu_init(). Reviewed-by: Pranjal Shrivastava Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 7eed5c8c72dd..07589350b2a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -16,6 +16,7 @@ #include struct arm_smmu_device; +struct arm_vsmmu; /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 @@ -720,6 +721,10 @@ struct arm_smmu_impl_ops { int (*init_structures)(struct arm_smmu_device *smmu); struct arm_smmu_cmdq *(*get_secondary_cmdq)( struct arm_smmu_device *smmu, struct arm_smmu_cmdq_ent *ent); + const size_t vsmmu_size; + const enum iommu_viommu_type vsmmu_type; + int (*vsmmu_init)(struct arm_vsmmu *vsmmu, + const struct iommu_user_data *user_data); }; /* An SMMUv3 instance */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index c14f7e6b4dae..445365ae19e0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -415,6 +415,10 @@ size_t arm_smmu_get_viommu_size(struct device *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return 0; + if (smmu->impl_ops && smmu->impl_ops->vsmmu_size && + viommu_type == smmu->impl_ops->vsmmu_type) + return smmu->impl_ops->vsmmu_size; + if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return 0; @@ -438,6 +442,10 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, /* FIXME Move VMID allocation from the S2 domain allocation to here */ vsmmu->vmid = s2_parent->s2_cfg.vmid; + if (smmu->impl_ops && smmu->impl_ops->vsmmu_init && + viommu->type == smmu->impl_ops->vsmmu_type) + return smmu->impl_ops->vsmmu_init(vsmmu, user_data); + viommu->ops = &arm_vsmmu_ops; return 0; }