| Message ID | 20250330210717.46080-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add support for DU and DSI on the Renesas RZ/V2H(P) SoC | expand |
On Sun, Mar 30, 2025 at 10:07:01PM +0100, Prabhakar wrote: > allOf: > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a07g044-du This goes probably after the if: block for renesas,r9a07g043u-du to keep sorting (if I get numbers correctly). > + then: > + properties: > + ports: > + properties: > + port@0: > + description: DSI > + port@1: > + description: DPI > + > + required: > + - port@0 > + - port@1 > - if: > properties: > compatible: > @@ -101,18 +119,20 @@ allOf: > > required: > - port@0 > - else: > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a09g057-du > + then: > properties: > ports: > properties: > port@0: > description: DSI port@1: false Best regards, Krzysztof
Hi Prabhakar, Thanks for your series! On Sun, 30 Mar 2025 at 23:08, Prabhakar <prabhakar.csengg@gmail.com> wrote: > Note, the clock patches aplly on top of the following patch series: > - https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > - https://lore.kernel.org/all/20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Same comment as on "[PATCH 0/6] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH". The first patch series was ultimately ignored because it was not clear how it related to other similar patches for the same driver; the second patch series is new, and depends on it. So please coordinate and resend, based on renesas-clk-for-v6.16, or even better, v6.15-rc1 next week. I may still review some clock patches (the ones that do not depend on pending new constructs) in this series this week, if time permits, but I won't apply them. Thanks! Gr{oetje,eeting}s, Geert
Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar <prabhakar.csengg@gmail.com> > Sent: 30 March 2025 22:07 > Subject: [PATCH 09/17] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication > and division by 8. The updated equation: > > hsfreq = (mode->clock * bpp) / (dsi->lanes); > > produces the same result while improving readability and clarity. > > Additionally, update the comment to clarify the relationship between HS clock bit frequency, HS byte > clock frequency, and HSFREQ. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Cheers, Biju > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz- > du/rzg2l_mipi_dsi.c > index c6f60b7f203b..746f82442c01 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -277,10 +277,10 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, > * hsclk: DSI HS Byte clock frequency (Hz) > * lanes: number of data lanes > * > - * hsclk(bit) = hsclk(byte) * 8 > + * hsclk(bit) = hsclk(byte) * 8 = hsfreq > */ > bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); > - hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); > + hsfreq = (mode->clock * bpp) / dsi->lanes; > > ret = pm_runtime_resume_and_get(dsi->dev); > if (ret < 0) > -- > 2.49.0
Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar <prabhakar.csengg@gmail.com> > Sent: 30 March 2025 22:07 > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to > pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt > dynamically to various SoC-specific requirements without hardcoding configurations. > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one on the RZ/G2L SoC. While > the LINK registers are shared between the two SoCs, the D-PHY registers differ. Also the VCLK range > differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is > introduced and as now passed as OF data. > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by allowing SoC-specific data > to be passed through OF. > > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 66 ++++++++++++++----- > .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 2 - > 2 files changed, 49 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz- > du/rzg2l_mipi_dsi.c > index e0379f099659..44b95082b29c 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -28,10 +28,24 @@ > > #include "rzg2l_mipi_dsi_regs.h" > > +struct rzg2l_mipi_dsi; > + > +struct rzg2l_mipi_dsi_hw_info { > + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); > + void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); > + u32 phy_reg_offset; > + u32 link_reg_offset; > + unsigned long max_dclk; > + unsigned long min_dclk; > + bool has_dphy_rstc; > +}; > + > struct rzg2l_mipi_dsi { > struct device *dev; > void __iomem *mmio; > > + const struct rzg2l_mipi_dsi_hw_info *info; > + > struct reset_control *rstc; > struct reset_control *arstc; > struct reset_control *prstc; > @@ -164,22 +178,22 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = { > > static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) { > - iowrite32(data, dsi->mmio + reg); > + iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); > } > > static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) { > - iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); > + iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg); > } > > static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg) { > - return ioread32(dsi->mmio + reg); > + return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg); > } > > static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) { > - return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); > + return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg); > } > > /* ----------------------------------------------------------------------------- > @@ -291,7 +305,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, > vclk_rate = clk_get_rate(dsi->vclk); > hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); > > - ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); > + ret = dsi->info->dphy_init(dsi, hsfreq); > if (ret < 0) > goto err_phy; > > @@ -334,7 +348,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, > return 0; > > err_phy: > - rzg2l_mipi_dsi_dphy_exit(dsi); > + dsi->info->dphy_exit(dsi); > pm_runtime_put(dsi->dev); > > return ret; > @@ -342,7 +356,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, > > static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi) { > - rzg2l_mipi_dsi_dphy_exit(dsi); > + dsi->info->dphy_exit(dsi); > pm_runtime_put(dsi->dev); > } > > @@ -585,10 +599,12 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, > const struct drm_display_info *info, > const struct drm_display_mode *mode) { > - if (mode->clock > 148500) > + struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); > + > + if (mode->clock > dsi->info->max_dclk) > return MODE_CLOCK_HIGH; > > - if (mode->clock < 5803) > + if (mode->clock < dsi->info->min_dclk) > return MODE_CLOCK_LOW; > > return MODE_OK; > @@ -714,6 +730,11 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > platform_set_drvdata(pdev, dsi); > dsi->dev = &pdev->dev; > > + dsi->info = of_device_get_match_data(&pdev->dev); > + if (!dsi->info) > + return dev_err_probe(dsi->dev, -ENODEV, > + "missing data info\n"); > + > ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); > if (ret < 0) > return dev_err_probe(dsi->dev, ret, > @@ -729,10 +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > if (IS_ERR(dsi->vclk)) > return PTR_ERR(dsi->vclk); > > - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > - if (IS_ERR(dsi->rstc)) > - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > - "failed to get rst\n"); > + if (dsi->info->has_dphy_rstc) { > + dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc. Cheers, Biju > + if (IS_ERR(dsi->rstc)) > + return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > + "failed to get rst\n"); > + } > > dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst"); > if (IS_ERR(dsi->arstc)) > @@ -757,13 +780,13 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > * mode->clock and format are not available. So initialize DPHY with > * timing parameters for 80Mbps. > */ > - ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000000); > + ret = dsi->info->dphy_init(dsi, 80000000); > if (ret < 0) > goto err_phy; > > txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR); > dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes); > - rzg2l_mipi_dsi_dphy_exit(dsi); > + dsi->info->dphy_exit(dsi); > pm_runtime_put(dsi->dev); > > /* Initialize the DRM bridge. */ > @@ -780,7 +803,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > return 0; > > err_phy: > - rzg2l_mipi_dsi_dphy_exit(dsi); > + dsi->info->dphy_exit(dsi); > pm_runtime_put(dsi->dev); > err_pm_disable: > pm_runtime_disable(dsi->dev); > @@ -795,8 +818,17 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev) > pm_runtime_disable(&pdev->dev); > } > > +static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { > + .dphy_init = rzg2l_mipi_dsi_dphy_init, > + .dphy_exit = rzg2l_mipi_dsi_dphy_exit, > + .has_dphy_rstc = true, > + .link_reg_offset = 0x10000, > + .max_dclk = 148500, > + .min_dclk = 5803, > +}; > + > static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { > - { .compatible = "renesas,rzg2l-mipi-dsi" }, > + { .compatible = "renesas,rzg2l-mipi-dsi", .data = > +&rzg2l_mipi_dsi_info, }, > { /* sentinel */ } > }; > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz- > du/rzg2l_mipi_dsi_regs.h > index 1dbc16ec64a4..16efe4dc59f4 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h > @@ -41,8 +41,6 @@ > #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) > > /* --------------------------------------------------------*/ > -/* Link Registers */ > -#define LINK_REG_OFFSET 0x10000 > > /* Link Status Register */ > #define LINKSR 0x10 > -- > 2.49.0
Hi Biju, Thank you for the review. On Mon, Mar 31, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > -----Original Message----- > > From: Prabhakar <prabhakar.csengg@gmail.com> > > Sent: 30 March 2025 22:07 > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to > > pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt > > dynamically to various SoC-specific requirements without hardcoding configurations. > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one on the RZ/G2L SoC. While > > the LINK registers are shared between the two SoCs, the D-PHY registers differ. Also the VCLK range > > differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is > > introduced and as now passed as OF data. > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by allowing SoC-specific data > > to be passed through OF. > > <snip> > > + > > ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); > > if (ret < 0) > > return dev_err_probe(dsi->dev, ret, > > @@ -729,10 +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > > if (IS_ERR(dsi->vclk)) > > return PTR_ERR(dsi->vclk); > > > > - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > > - if (IS_ERR(dsi->rstc)) > > - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > > - "failed to get rst\n"); > > + if (dsi->info->has_dphy_rstc) { > > + dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc. > As the dtbs_check doesn't enforce this, `has_dphy_rstc` flag was added. Recently the same was done for the CRU [0] based on the recent comment received. [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20250328173032.423322-10-tommaso.merciai.xr@bp.renesas.com/ Cheers, Prabhakar
Hi Geert, Thank you for the review. On Mon, Mar 31, 2025 at 1:29 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Sun, 30 Mar 2025 at 23:08, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Introduce the `RZ_MIPI_DSI_16BPP` feature flag in `rzg2l_mipi_dsi_hw_info` > > to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports > > 16BPP, whereas this feature is missing on the RZ/G2L SoC. > > > > Update the `mipi_dsi_host_attach()` function to check this flag before > > allowing 16BPP formats. If the SoC does not support 16BPP, return an error > > to prevent incorrect format selection. > > > > This change enables finer-grained format support control for different > > SoC variants. > > > > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > @@ -30,6 +30,8 @@ > > > > struct rzg2l_mipi_dsi; > > > > +#define RZ_MIPI_DSI_16BPP BIT(0) > > + > > struct rzg2l_mipi_dsi_hw_info { > > int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz); > > void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); > > @@ -38,6 +40,7 @@ struct rzg2l_mipi_dsi_hw_info { > > unsigned long max_dclk; > > unsigned long min_dclk; > > bool has_dphy_rstc; > > + u8 features; > > Please settle on a single solution for all features: either use a > boolean flag to indicate 16bpp, or a feature bit to indicate the need > for the DPHY reset signal. > Agreed, I will use the features flag for all. Cheers, Prabhakar
> -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: 31 March 2025 14:59 > To: Biju Das <biju.das.jz@bp.renesas.com> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Andrzej Hajda <andrzej.hajda@intel.com>; Neil > Armstrong <neil.armstrong@linaro.org>; Robert Foss <rfoss@kernel.org>; laurent.pinchart > <laurent.pinchart@ideasonboard.com>; Jonas Karlman <jonas@kwiboo.se>; Jernej Skrabec > <jernej.skrabec@gmail.com>; David Airlie <airlied@gmail.com>; Simona Vetter <simona@ffwll.ch>; Maarten > Lankhorst <maarten.lankhorst@linux.intel.com>; Maxime Ripard <mripard@kernel.org>; Thomas Zimmermann > <tzimmermann@suse.de>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor > Dooley <conor+dt@kernel.org>; Mauro Carvalho Chehab <mchehab@kernel.org>; Kieran Bingham > <kieran.bingham+renesas@ideasonboard.com>; Stephen Boyd <sboyd@kernel.org>; Philipp Zabel > <p.zabel@pengutronix.de>; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-renesas- > soc@vger.kernel.org; linux-media@vger.kernel.org; linux-clk@vger.kernel.org; Fabrizio Castro > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support > > Hi Biju, > > Thank you for the review. > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > Hi Prabhakar, > > > > Thanks for the patch. > > > > > -----Original Message----- > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: 30 March 2025 22:07 > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data > > > support > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC, > > > this patch introduces a mechanism to pass SoC-specific information > > > via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC- > specific requirements without hardcoding configurations. > > > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to > > > the one on the RZ/G2L SoC. While the LINK registers are shared > > > between the two SoCs, the D-PHY registers differ. Also the VCLK > > > range differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` > is introduced and as now passed as OF data. > > > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC > > > support by allowing SoC-specific data to be passed through OF. > > > > <snip> > > > + > > > ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); > > > if (ret < 0) > > > return dev_err_probe(dsi->dev, ret, @@ -729,10 +750,12 > > > @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > > > if (IS_ERR(dsi->vclk)) > > > return PTR_ERR(dsi->vclk); > > > > > > - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > > > - if (IS_ERR(dsi->rstc)) > > > - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > > > - "failed to get rst\n"); > > > + if (dsi->info->has_dphy_rstc) { > > > + dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, > > > + "rst"); > > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc. > > > As the dtbs_check doesn't enforce this, `has_dphy_rstc` flag was added. Recently the same was done > for the CRU [0] based on the recent comment received. > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning, right? Cheers, Biju
Hi Biju, On Mon, Mar 31, 2025 at 3:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > -----Original Message----- > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > Sent: 31 March 2025 14:59 > > To: Biju Das <biju.das.jz@bp.renesas.com> > > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Andrzej Hajda <andrzej.hajda@intel.com>; Neil > > Armstrong <neil.armstrong@linaro.org>; Robert Foss <rfoss@kernel.org>; laurent.pinchart > > <laurent.pinchart@ideasonboard.com>; Jonas Karlman <jonas@kwiboo.se>; Jernej Skrabec > > <jernej.skrabec@gmail.com>; David Airlie <airlied@gmail.com>; Simona Vetter <simona@ffwll.ch>; Maarten > > Lankhorst <maarten.lankhorst@linux.intel.com>; Maxime Ripard <mripard@kernel.org>; Thomas Zimmermann > > <tzimmermann@suse.de>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor > > Dooley <conor+dt@kernel.org>; Mauro Carvalho Chehab <mchehab@kernel.org>; Kieran Bingham > > <kieran.bingham+renesas@ideasonboard.com>; Stephen Boyd <sboyd@kernel.org>; Philipp Zabel > > <p.zabel@pengutronix.de>; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-renesas- > > soc@vger.kernel.org; linux-media@vger.kernel.org; linux-clk@vger.kernel.org; Fabrizio Castro > > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support > > > > Hi Biju, > > > > Thank you for the review. > > > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > Hi Prabhakar, > > > > > > Thanks for the patch. > > > > > > > -----Original Message----- > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > Sent: 30 March 2025 22:07 > > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data > > > > support > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC, > > > > this patch introduces a mechanism to pass SoC-specific information > > > > via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC- > > specific requirements without hardcoding configurations. > > > > > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to > > > > the one on the RZ/G2L SoC. While the LINK registers are shared > > > > between the two SoCs, the D-PHY registers differ. Also the VCLK > > > > range differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` > > is introduced and as now passed as OF data. > > > > > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC > > > > support by allowing SoC-specific data to be passed through OF. > > > > > > <snip> > > > > + > > > > ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); > > > > if (ret < 0) > > > > return dev_err_probe(dsi->dev, ret, @@ -729,10 +750,12 > > > > @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > > > > if (IS_ERR(dsi->vclk)) > > > > return PTR_ERR(dsi->vclk); > > > > > > > > - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > > > > - if (IS_ERR(dsi->rstc)) > > > > - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > > > > - "failed to get rst\n"); > > > > + if (dsi->info->has_dphy_rstc) { > > > > + dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, > > > > + "rst"); > > > > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc. > > > > > As the dtbs_check doesn't enforce this, `has_dphy_rstc` flag was added. Recently the same was done > > for the CRU [0] based on the recent comment received. > > > > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning, right? > No we dont [0], note DT binding is written based on the recent feedback received. [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20250330210717.46080-7-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar
Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: 31 March 2025 15:44 > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support > > Hi Biju, > > On Mon, Mar 31, 2025 at 3:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > -----Original Message----- > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: 31 March 2025 14:59 > > > To: Biju Das <biju.das.jz@bp.renesas.com> > > > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Andrzej Hajda > > > <andrzej.hajda@intel.com>; Neil Armstrong > > > <neil.armstrong@linaro.org>; Robert Foss <rfoss@kernel.org>; > > > laurent.pinchart <laurent.pinchart@ideasonboard.com>; Jonas Karlman > > > <jonas@kwiboo.se>; Jernej Skrabec <jernej.skrabec@gmail.com>; David > > > Airlie <airlied@gmail.com>; Simona Vetter <simona@ffwll.ch>; Maarten > > > Lankhorst <maarten.lankhorst@linux.intel.com>; Maxime Ripard > > > <mripard@kernel.org>; Thomas Zimmermann <tzimmermann@suse.de>; Rob > > > Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; > > > Conor Dooley <conor+dt@kernel.org>; Mauro Carvalho Chehab > > > <mchehab@kernel.org>; Kieran Bingham > > > <kieran.bingham+renesas@ideasonboard.com>; Stephen Boyd > > > <sboyd@kernel.org>; Philipp Zabel <p.zabel@pengutronix.de>; > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > > > linux-renesas- soc@vger.kernel.org; linux-media@vger.kernel.org; > > > linux-clk@vger.kernel.org; Fabrizio Castro > > > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF > > > data support > > > > > > Hi Biju, > > > > > > Thank you for the review. > > > > > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > Hi Prabhakar, > > > > > > > > Thanks for the patch. > > > > > > > > > -----Original Message----- > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > Sent: 30 March 2025 22:07 > > > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF > > > > > data support > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC, > > > > > this patch introduces a mechanism to pass SoC-specific > > > > > information via OF data in the DSI driver. This enables the > > > > > driver to adapt dynamically to various SoC- > > > specific requirements without hardcoding configurations. > > > > > > > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical > > > > > to the one on the RZ/G2L SoC. While the LINK registers are > > > > > shared between the two SoCs, the D-PHY registers differ. Also > > > > > the VCLK range differs on both these SoCs. To accommodate these > > > > > differences `struct rzg2l_mipi_dsi_hw_info` > > > is introduced and as now passed as OF data. > > > > > > > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC > > > > > support by allowing SoC-specific data to be passed through OF. > > > > > > > > <snip> > > > > > + > > > > > ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); > > > > > if (ret < 0) > > > > > return dev_err_probe(dsi->dev, ret, @@ -729,10 > > > > > +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > > > > > if (IS_ERR(dsi->vclk)) > > > > > return PTR_ERR(dsi->vclk); > > > > > > > > > > - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > > > > > - if (IS_ERR(dsi->rstc)) > > > > > - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > > > > > - "failed to get rst\n"); > > > > > + if (dsi->info->has_dphy_rstc) { > > > > > + dsi->rstc = > > > > > + devm_reset_control_get_exclusive(dsi->dev, > > > > > + "rst"); > > > > > > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc. > > > > > > > As the dtbs_check doesn't enforce this, `has_dphy_rstc` flag was > > > added. Recently the same was done for the CRU [0] based on the recent comment received. > > > > > > > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning, > right? > > > No we dont [0], note DT binding is written based on the recent feedback received. That is strange. It is triggering warning for me, if I just update the example. from schema $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# /home/biju/rzg3e-linux-renesas/Documentation/devicetree/bindings/display/bridge/renesas,dsi.example.dtb: dsi@10850000: reset-names: ['rst', 'arst', 'prst'] is too long from schema $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# [1] dsi0: dsi@10850000 { - compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi"; + compatible = "renesas,r9a09g057-mipi-dsi"; reg = <0x10850000 0x20000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -205,12 +205,11 @@ examples: interrupt-names = "seq0", "seq1", "vin1", "rcv", "ferr", "ppi", "debug"; clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, - <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; - clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + clock-names = "pllclk", "aclk", "pclk", "vclk", "lpclk"; resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, <&cpg R9A07G044_MIPI_DSI_ARESET_N>, <&cpg R9A07G044_MIPI_DSI_PRESET_N>; reset-names = "rst", "arst", "prst"; Cheers, Biju > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20250330210717.46080-7- > prabhakar.mahadev-lad.rj@bp.renesas.com/ > > Cheers, > Prabhakar
Hi Biju, On Mon, Mar 31, 2025 at 4:04 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > > -----Original Message----- > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > Sent: 31 March 2025 15:44 > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF data support > > > > Hi Biju, > > > > On Mon, Mar 31, 2025 at 3:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > > > > > -----Original Message----- > > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > > Sent: 31 March 2025 14:59 > > > > To: Biju Das <biju.das.jz@bp.renesas.com> > > > > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Andrzej Hajda > > > > <andrzej.hajda@intel.com>; Neil Armstrong > > > > <neil.armstrong@linaro.org>; Robert Foss <rfoss@kernel.org>; > > > > laurent.pinchart <laurent.pinchart@ideasonboard.com>; Jonas Karlman > > > > <jonas@kwiboo.se>; Jernej Skrabec <jernej.skrabec@gmail.com>; David > > > > Airlie <airlied@gmail.com>; Simona Vetter <simona@ffwll.ch>; Maarten > > > > Lankhorst <maarten.lankhorst@linux.intel.com>; Maxime Ripard > > > > <mripard@kernel.org>; Thomas Zimmermann <tzimmermann@suse.de>; Rob > > > > Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; > > > > Conor Dooley <conor+dt@kernel.org>; Mauro Carvalho Chehab > > > > <mchehab@kernel.org>; Kieran Bingham > > > > <kieran.bingham+renesas@ideasonboard.com>; Stephen Boyd > > > > <sboyd@kernel.org>; Philipp Zabel <p.zabel@pengutronix.de>; > > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > > > > linux-renesas- soc@vger.kernel.org; linux-media@vger.kernel.org; > > > > linux-clk@vger.kernel.org; Fabrizio Castro > > > > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Subject: Re: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF > > > > data support > > > > > > > > Hi Biju, > > > > > > > > Thank you for the review. > > > > > > > > On Mon, Mar 31, 2025 at 1:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > > Hi Prabhakar, > > > > > > > > > > Thanks for the patch. > > > > > > > > > > > -----Original Message----- > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > Sent: 30 March 2025 22:07 > > > > > > Subject: [PATCH 11/17] drm: renesas: rz-du: mipi_dsi: Add OF > > > > > > data support > > > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > In preparation for adding support for the Renesas RZ/V2H(P) SoC, > > > > > > this patch introduces a mechanism to pass SoC-specific > > > > > > information via OF data in the DSI driver. This enables the > > > > > > driver to adapt dynamically to various SoC- > > > > specific requirements without hardcoding configurations. > > > > > > > > > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical > > > > > > to the one on the RZ/G2L SoC. While the LINK registers are > > > > > > shared between the two SoCs, the D-PHY registers differ. Also > > > > > > the VCLK range differs on both these SoCs. To accommodate these > > > > > > differences `struct rzg2l_mipi_dsi_hw_info` > > > > is introduced and as now passed as OF data. > > > > > > > > > > > > These changes lay the groundwork for the upcoming RZ/V2H(P) SoC > > > > > > support by allowing SoC-specific data to be passed through OF. > > > > > > > > > > <snip> > > > > > > + > > > > > > ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); > > > > > > if (ret < 0) > > > > > > return dev_err_probe(dsi->dev, ret, @@ -729,10 > > > > > > +750,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) > > > > > > if (IS_ERR(dsi->vclk)) > > > > > > return PTR_ERR(dsi->vclk); > > > > > > > > > > > > - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); > > > > > > - if (IS_ERR(dsi->rstc)) > > > > > > - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), > > > > > > - "failed to get rst\n"); > > > > > > + if (dsi->info->has_dphy_rstc) { > > > > > > + dsi->rstc = > > > > > > + devm_reset_control_get_exclusive(dsi->dev, > > > > > > + "rst"); > > > > > > > > > > Maybe use devm_reset_control_get_optional_exclusive by dropping has_dphy_rstc. > > > > > > > > > As the dtbs_check doesn't enforce this, `has_dphy_rstc` flag was > > > > added. Recently the same was done for the CRU [0] based on the recent comment received. > > > > > > > > > > RZ/V2H has "arst" and "prst". So, If you add "rst" for RZ/V2H then you should get dtbs warning, > > right? > > > > > No we dont [0], note DT binding is written based on the recent feedback received. > > That is strange. It is triggering warning for me, if I just update the example. > Ahh right I missed that. The current implementation is based on this comment received [0] (same being applied for reset). Please let me know if you still want me to use devm_reset_control_get_optional_exclusive() (and same for the clk). [0] https://lore.kernel.org/lkml/20250223181955.GD8330@pendragon.ideasonboard.com/ Cheers, Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, This patch series adds support for the Display Unit (DU) and MIPI DSI interface on the Renesas RZ/V2H(P) SoC. The inital patches add PLLDSI clocks and reset entries for the DSI and LCDC and the later patches add support for the DU and DSI drivers. The DU block is similar to the RZ/G2L SoC, but the DSI interface is slightly different. The patches include updates to the device tree bindings, clock and reset controllers, and the DU driver to accommodate these changes. Note, my initail intention was to split the clock patches and the DU/DSI driver patches into two separate series. However, I found that sending them together will make it easier for the reviewers to understand clock related changes. Note, the clock patches aplly on top of the following patch series: - https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ - https://lore.kernel.org/all/20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (17): clk: renesas: rzv2h-cpg: Add support for DSI clocks clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC media: dt-bindings: media: renesas,vsp1: Document RZ/V2H(P) media: dt-bindings: media: renesas,fcp: Document RZ/V2H(P) SoC dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC drm: renesas: rz-du: Add support for RZ/V2H(P) SoC drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation drm: renesas: rz-du: mipi_dsi: Add OF data support drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC .../bindings/display/bridge/renesas,dsi.yaml | 117 +++- .../bindings/display/renesas,rzg2l-du.yaml | 28 +- .../bindings/media/renesas,fcp.yaml | 2 + .../bindings/media/renesas,vsp1.yaml | 1 + drivers/clk/renesas/r9a09g057-cpg.c | 63 ++ drivers/clk/renesas/rzv2h-cpg.c | 284 ++++++++ drivers/clk/renesas/rzv2h-cpg.h | 17 + drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 + .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 607 +++++++++++++++++- .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 42 +- include/linux/clk/renesas-rzv2h-dsi.h | 207 ++++++ 11 files changed, 1309 insertions(+), 70 deletions(-) create mode 100644 include/linux/clk/renesas-rzv2h-dsi.h