[0/8] media: imx-mipi-csis: Cleanups and debugging improvements

Hello,

This patch series bring a few miscellaneous improvements to the
imx-mipi-csis driver, and in particular improves the debugging
infrastructure.

Patch 1/8 starts by aligning the code with the reference manual for
register field names, increasing readability of the driver when read
alongside the hardware documentation. Patch 2/8 then fixes a small
alignment issue in register dumps. Patch 3/8 logs per-lane start of
transmission error instead of supporting the first data lane only,
easing debugging of D-PHY issues.

The next two patches deprecate the clock-frequency DT property, which
shouldn't have been added in the first place. Patch 4/8 improves
handling of the clock frequency in the driver, and patch 5/8 deprecates
the property in the DT bindings. The driver still supports the property
to ensure backward compatibility.

The last three patches introduce support for multiple output channels
and wire it up in the debugging infrastructure. The CSIS IP core
supports up to 4 output channels, with the number of instantiated
channels being a property of the SoC integration. So far, only the
i.MX8MP is known to have multiple output channels. Patch 6/8 adds a
corresponding DT property, and patch 7/8 sets it in the i.MX8MP DT.
Patch 8/8 then adds initial support for that property in the driver, and
uses it to dump per-channel registers and event counters.

Laurent Pinchart (8):
  media: imx-mipi-csis: Rename register macros to match reference manual
  media: imx-mipi-csis: Fix field alignment in register dump
  media: imx-mipi-csis: Log per-lane start of transmission errors
  media: imx-mipi-csis: Only set clock rate when specified in DT
  dt-bindings: media: nxp,imx-mipi-csi2: Mark clock-frequency as
    deprecated
  dt-bindings: media: nxp,imx-mipi-csi2: Add fsl,num-channels property
  arm64: dts: imx8mp: Specify the number of channels for CSI-2 receivers
  media: imx-mipi-csis: Initial support for multiple output channels

 .../bindings/media/nxp,imx-mipi-csi2.yaml     |  18 +-
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     |   2 +
 drivers/media/platform/nxp/imx-mipi-csis.c    | 311 +++++++++++-------
 3 files changed, 211 insertions(+), 120 deletions(-)


base-commit: 3c699df678515355e871141e142adae3bbf44216
prerequisite-patch-id: 7200af6e6d693b425b5cdb9ae6be1c55e23e2a45

On Mon, Jun 09, 2025 at 02:58:37AM +0300, Laurent Pinchart wrote:
> Usage of the clock-frequency property, which is already optional, is
> discouraged in favour of using assigned-clock-rates (and
> assigned-clock-parents where needed). Mark the property as deprecated,
> and update the examples accordingly.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  .../devicetree/bindings/media/nxp,imx-mipi-csi2.yaml  | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> index 03a23a26c4f3..db4889bf881e 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> @@ -66,6 +66,7 @@ properties:
>    clock-frequency:
>      description: The desired external clock ("wrap") frequency, in Hz
>      default: 166000000
> +    deprecated: true
>
>    ports:
>      $ref: /schemas/graph.yaml#/properties/ports
> @@ -147,7 +148,9 @@ examples:
>                   <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
>                   <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
>          clock-names = "pclk", "wrap", "phy";
> -        clock-frequency = <166000000>;
> +
> +        assigned-clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>;
> +        assigned-clock-rates = <166000000>;
>
>          power-domains = <&pgc_mipi_phy>;
>          phy-supply = <&reg_1p0d>;
> @@ -185,12 +188,16 @@ examples:
>          compatible = "fsl,imx8mm-mipi-csi2";
>          reg = <0x32e30000 0x1000>;
>          interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> -        clock-frequency = <333000000>;
> +
>          clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
>                   <&clk IMX8MM_CLK_CSI1_ROOT>,
>                   <&clk IMX8MM_CLK_CSI1_PHY_REF>,
>                   <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
>          clock-names = "pclk", "wrap", "phy", "axi";
> +
> +        assigned-clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
> +        assigned-clock-rates = <250000000>;
> +
>          power-domains = <&mipi_pd>;
>
>          ports {
> --
> Regards,
>
> Laurent Pinchart
>