From patchwork Sat Jul 17 08:12:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 479451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17EB5C636CE for ; Sat, 17 Jul 2021 08:12:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01DB3613D9 for ; Sat, 17 Jul 2021 08:12:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232832AbhGQIPt (ORCPT ); Sat, 17 Jul 2021 04:15:49 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:56350 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229863AbhGQIPl (ORCPT ); Sat, 17 Jul 2021 04:15:41 -0400 X-UUID: 93cf79a8e21548ac9ad862ab5cfeaac7-20210717 X-UUID: 93cf79a8e21548ac9ad862ab5cfeaac7-20210717 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 414781194; Sat, 17 Jul 2021 16:12:42 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 17 Jul 2021 16:12:41 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 17 Jul 2021 16:12:40 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: Hsin-Yi Wang , Fritz Koenig , Irui Wang , , , , , , , Subject: [PATCH v2, 04/14] dt-bindings: media: mtk-vcodec: Separate video encoder and decoder dt-bindings Date: Sat, 17 Jul 2021 16:12:23 +0800 Message-ID: <20210717081233.7809-5-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210717081233.7809-1-yunfei.dong@mediatek.com> References: <20210717081233.7809-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Decoder will use component framework to manage hardware, it is big difference with encoder. Signed-off-by: Yunfei Dong --- v2: Remove useless code for this patch. --- ...vcodec.txt => mediatek-vcodec-decoder.txt} | 62 ++-------------- .../media/mediatek-vcodec-encoder.txt | 73 +++++++++++++++++++ 2 files changed, 79 insertions(+), 56 deletions(-) rename Documentation/devicetree/bindings/media/{mediatek-vcodec.txt => mediatek-vcodec-decoder.txt} (56%) create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec-encoder.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec-decoder.txt similarity index 56% rename from Documentation/devicetree/bindings/media/mediatek-vcodec.txt rename to Documentation/devicetree/bindings/media/mediatek-vcodec-decoder.txt index c44a6e6943af..7c6e608df8a9 100644 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec-decoder.txt @@ -1,26 +1,20 @@ -Mediatek Video Codec +Mediatek Video Decoder -Mediatek Video Codec is the video codec hw present in Mediatek SoCs which -supports high resolution encoding and decoding functionalities. +Mediatek Video Decoder is the video decode hw present in Mediatek SoCs which +supports high resolution decoding functionalities. Required properties: - compatible : must be one of the following string: - "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder. - "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder. - "mediatek,mt8183-vcodec-enc" for MT8183 encoder. "mediatek,mt8173-vcodec-dec" for MT8173 decoder. - "mediatek,mt8192-vcodec-enc" for MT8192 encoder. "mediatek,mt8183-vcodec-dec" for MT8183 decoder. -- reg : Physical base address of the video codec registers and length of +- reg : Physical base address of the video decoder registers and length of memory mapped region. - interrupts : interrupt number to the cpu. - mediatek,larb : must contain the local arbiters in the current Socs. - clocks : list of clock specifiers, corresponding to entries in the clock-names property. -- clock-names: avc encoder must contain "venc_sel", vp8 encoder must - contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2", - "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", - "vdec_bus_clk_src". +- clock-names: must contain "vcodecpll", "univpll_d2", "clk_cci400_sel" + "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src". - iommus : should point to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. @@ -84,47 +78,3 @@ vcodec_dec: vcodec@16000000 { <&topckgen CLK_TOP_VCODECPLL>; assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; }; - -vcodec_enc_avc: vcodec@18002000 { - compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>; - interrupts = ; - iommus = <&iommu M4U_PORT_VENC_RCPU>, - <&iommu M4U_PORT_VENC_REC>, - <&iommu M4U_PORT_VENC_BSDMA>, - <&iommu M4U_PORT_VENC_SV_COMV>, - <&iommu M4U_PORT_VENC_RD_COMV>, - <&iommu M4U_PORT_VENC_CUR_LUMA>, - <&iommu M4U_PORT_VENC_CUR_CHROMA>, - <&iommu M4U_PORT_VENC_REF_LUMA>, - <&iommu M4U_PORT_VENC_REF_CHROMA>, - <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>; - mediatek,larb = <&larb3>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENC_SEL>; - clock-names = "venc_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; - }; - -vcodec_enc_vp8: vcodec@19002000 { - compatible = "mediatek,mt8173-vcodec-enc-vp8"; - reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = ; - iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,larb = <&larb5>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec-encoder.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec-encoder.txt new file mode 100644 index 000000000000..81c47fd44958 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec-encoder.txt @@ -0,0 +1,73 @@ +Mediatek Video Encoder + +Mediatek Video Encoder is the video encode hw present in Mediatek SoCs which +supports high resolution encoding functionalities. + +Required properties: +- compatible : must be one of the following string: + "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder. + "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder. + "mediatek,mt8183-vcodec-enc" for MT8183 encoder. + "mediatek,mt8192-vcodec-enc" for MT8192 encoder. +- reg : Physical base address of the video encoder registers and length of + memory mapped region. +- interrupts : interrupt number to the cpu. +- mediatek,larb : must contain the local arbiters in the current Socs. +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property. +- clock-names: avc encoder must contain "venc_sel", vp8 encoder must + contain "venc_lt_sel". +- iommus : should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml + for details. +- dma-ranges : describes the dma address range space that the codec hw access. +One of the two following nodes: +- mediatek,vpu : the node of the video processor unit, if using VPU. +- mediatek,scp : the node of the SCP unit, if using SCP. + + +Example: + +vcodec_enc_avc: vcodec@18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>; + interrupts = ; + iommus = <&iommu M4U_PORT_VENC_RCPU>, + <&iommu M4U_PORT_VENC_REC>, + <&iommu M4U_PORT_VENC_BSDMA>, + <&iommu M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_PORT_VENC_NBM_WDMA>; + mediatek,larb = <&larb3>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + }; + +vcodec_enc_vp8: vcodec@19002000 { + compatible = "mediatek,mt8173-vcodec-enc-vp8"; + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = ; + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,larb = <&larb5>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; + };