new file mode 100644
@@ -0,0 +1,218 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Video Encoder Accelerator With Multi Core
+
+maintainers:
+ - Irui Wang <irui.wang@mediatek.com>
+
+description: |
+ MediaTek Video Encoder is the video encoder hardware present in MediaTek
+ SoCs which supports high resolution encoding functionalities. To meet higher
+ encoder performance, there will be one or more encoder hardware inside SoC,
+ which named core0, core1, etc.. For example, mt8195 has two encoder hardware,
+ the two encoder cores block diagram, can check below.
+ --------------------------------------------------------------
+ Input frame 0 1 2 3 4 5 6
+ | | | | | | |
+ v | v | v | v
+ +-------+ | +-------+ | +-------+ | +-------+
+ | core0 | | | core0 | | | core0 | | | core0 |
+ +-------+ | +-------+ | +-------+ | +-------+
+ | | | | | | |
+ | v | v | v |
+ | +-------+ | +-------+ | +-------+ |
+ | | core1 | | | core1 | | | core1 | |
+ | +-------+ | +-------+ | +-------+ |
+ | | | | | | |
+ v v v v v v v <parent>
+ --------------------------------------------------------------
+ core || index <child>
+ \/
+ +--------------------------------------------------+
+ | core0/core1 |
+ | enable/disable power/clk/irq |
+ +--------------------------------------------------+
+ --------------------------------------------------------------
+ As above, there are two cores child devices, they are two encoder hardware
+ which can encode input frames in order. When start encoding, input frame 0
+ will be encoded by core0, and input frame 1 can be encoded by core1 even if
+ frame 0 has not been encoded done yet, after frame 0 encoded done, frame 2
+ will be encoded by core0, even input frames are encoded by core0 and odd
+ input frames are encoded by core1, these two encoder cores encode ench input
+ frames in this overlapping manner.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-vcodec-enc
+
+ reg:
+ maxItems: 1
+
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ The node of system control processor (SCP), using
+ the remoteproc & rpmsg framework.
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ dma-ranges:
+ maxItems: 1
+ description: |
+ Describes the physical address space of IOMMU maps to memory.
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+# Required child node:
+patternProperties:
+ "^venc-core@[0-9a-f]+$":
+ type: object
+ description: |
+ The video encoder core device node which should be added as subnodes to
+ the main venc node, it represents a encoder hardware.
+
+ properties:
+ compatible:
+ items:
+ - const: mediatek,mtk-venc-hw
+
+ reg:
+ maxItems: 1
+
+ mediatek,hw-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Current encoder core id. We use it to pick which one encoder core
+ will be used to encoding current input frame.
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - mediatek,hw-id
+ - iommus
+ - interrupts
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - power-domains
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - mediatek,scp
+ - iommus
+ - interrupts
+ - clocks
+ - clock-names
+ - dma-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/mt8195-memory-port.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ venc: venc@1a020000 {
+ compatible = "mediatek,mt8195-vcodec-enc";
+ reg = <0 0x1a020000 0 0x10000>;
+ mediatek,scp = <&scp>;
+ iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
+ <&iommu_vdo M4U_PORT_L19_VENC_REC>,
+ <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
+ <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
+ <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vencsys CLK_VENC_VENC>;
+ clock-names = "clk_venc";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ venc-core@1b020000 {
+ compatible = "mediatek,mtk-venc-hw";
+ reg = <0 0x1b020000 0 0x10000>;
+ mediatek,hw-id = <1>;
+ iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>,
+ <&iommu_vpp M4U_PORT_L20_VENC_REC>,
+ <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>,
+ <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>,
+ <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>,
+ <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>,
+ <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>,
+ <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>,
+ <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>;
+ clock-names = "clk_venc_core1";
+ assigned-clocks = <&topckgen CLK_TOP_VENC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+ };
+ };
+ };
@@ -21,7 +21,6 @@ properties:
- mediatek,mt8173-vcodec-enc
- mediatek,mt8183-vcodec-enc
- mediatek,mt8192-vcodec-enc
- - mediatek,mt8195-vcodec-enc
reg:
maxItems: 1
mt8195 has two H264 encoder hardware, which are named core0 and core1. The two encoder cores are independent, we can just enable one core to do encoding or enable both of them to achieve higher performance. We pick core0 as main device and core1 as its subdevice, it just a way to to manage the two encoder hardware, because they are two equal encoder hardware with the same function. Signed-off-by: Irui Wang <irui.wang@mediatek.com> --- .../media/mediatek,vcodec-encoder-core.yaml | 218 ++++++++++++++++++ .../media/mediatek,vcodec-encoder.yaml | 1 - 2 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml