From patchwork Fri Jul 29 03:51:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Irui Wang X-Patchwork-Id: 595752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D003C19F2B for ; Fri, 29 Jul 2022 03:51:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234183AbiG2Dvo (ORCPT ); Thu, 28 Jul 2022 23:51:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234135AbiG2Dvm (ORCPT ); Thu, 28 Jul 2022 23:51:42 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 717BB7CB66; Thu, 28 Jul 2022 20:51:40 -0700 (PDT) X-UUID: d5ca703262624e17a5cb8be3c48eeb7a-20220729 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:e72b269b-5486-41dd-8d36-1c3c2bf9f80b, OB:0, LO B:0,IP:0,URL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:20 X-CID-META: VersionHash:0f94e32, CLOUDID:a433b5cf-a6cf-4fb6-be1b-c60094821ca2, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: d5ca703262624e17a5cb8be3c48eeb7a-20220729 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 539634473; Fri, 29 Jul 2022 11:51:34 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 29 Jul 2022 11:51:32 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 29 Jul 2022 11:51:31 +0800 From: Irui Wang To: Hans Verkuil , , Rob Herring , Mauro Carvalho Chehab , Matthias Brugger , Alexandre Courbot , "Tiffany Lin" , Andrew-CT Chen , Tzung-Bi Shih , Tomasz Figa , CC: Maoguang Meng , Longfei Wang , Yunfei Dong , "Irui Wang" , , , , , , Subject: [PATCH v5, 1/8] dt-bindings: media: mediatek: vcodec: Adds encoder cores dt-bindings for mt8195 Date: Fri, 29 Jul 2022 11:51:22 +0800 Message-ID: <20220729035129.3634-2-irui.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220729035129.3634-1-irui.wang@mediatek.com> References: <20220729035129.3634-1-irui.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org mt8195 has two H264 encoder hardware, which are named core0 and core1. The two encoder cores are independent, we can just enable one core to do encoding or enable both of them to achieve higher performance. We pick core0 as main device and core1 as its subdevice, it just a way to to manage the two encoder hardware, because they are two equal encoder hardware with the same function. Signed-off-by: Irui Wang --- .../media/mediatek,vcodec-encoder-core.yaml | 218 ++++++++++++++++++ .../media/mediatek,vcodec-encoder.yaml | 1 - 2 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml new file mode 100644 index 000000000000..96e016f5000b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder-core.yaml @@ -0,0 +1,218 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/mediatek,vcodec-encoder-core.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Video Encoder Accelerator With Multi Core + +maintainers: + - Irui Wang + +description: | + MediaTek Video Encoder is the video encoder hardware present in MediaTek + SoCs which supports high resolution encoding functionalities. To meet higher + encoder performance, there will be one or more encoder hardware inside SoC, + which named core0, core1, etc.. For example, mt8195 has two encoder hardware, + the two encoder cores block diagram, can check below. + -------------------------------------------------------------- + Input frame 0 1 2 3 4 5 6 + | | | | | | | + v | v | v | v + +-------+ | +-------+ | +-------+ | +-------+ + | core0 | | | core0 | | | core0 | | | core0 | + +-------+ | +-------+ | +-------+ | +-------+ + | | | | | | | + | v | v | v | + | +-------+ | +-------+ | +-------+ | + | | core1 | | | core1 | | | core1 | | + | +-------+ | +-------+ | +-------+ | + | | | | | | | + v v v v v v v + -------------------------------------------------------------- + core || index + \/ + +--------------------------------------------------+ + | core0/core1 | + | enable/disable power/clk/irq | + +--------------------------------------------------+ + -------------------------------------------------------------- + As above, there are two cores child devices, they are two encoder hardware + which can encode input frames in order. When start encoding, input frame 0 + will be encoded by core0, and input frame 1 can be encoded by core1 even if + frame 0 has not been encoded done yet, after frame 0 encoded done, frame 2 + will be encoded by core0, even input frames are encoded by core0 and odd + input frames are encoded by core1, these two encoder cores encode ench input + frames in this overlapping manner. + +properties: + compatible: + items: + - enum: + - mediatek,mt8195-vcodec-enc + + reg: + maxItems: 1 + + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + The node of system control processor (SCP), using + the remoteproc & rpmsg framework. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + dma-ranges: + maxItems: 1 + description: | + Describes the physical address space of IOMMU maps to memory. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^venc-core@[0-9a-f]+$": + type: object + description: | + The video encoder core device node which should be added as subnodes to + the main venc node, it represents a encoder hardware. + + properties: + compatible: + items: + - const: mediatek,mtk-venc-hw + + reg: + maxItems: 1 + + mediatek,hw-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Current encoder core id. We use it to pick which one encoder core + will be used to encoding current input frame. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - mediatek,hw-id + - iommus + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - power-domains + + additionalProperties: false + +required: + - compatible + - reg + - mediatek,scp + - iommus + - interrupts + - clocks + - clock-names + - dma-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + venc: venc@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = ; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "clk_venc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + venc-core@1b020000 { + compatible = "mediatek,mtk-venc-hw"; + reg = <0 0x1b020000 0 0x10000>; + mediatek,hw-id = <1>; + iommus = <&iommu_vpp M4U_PORT_L20_VENC_RCPU>, + <&iommu_vpp M4U_PORT_L20_VENC_REC>, + <&iommu_vpp M4U_PORT_L20_VENC_BSDMA>, + <&iommu_vpp M4U_PORT_L20_VENC_SV_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_RD_COMV>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_CUR_CHROMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_LUMA>, + <&iommu_vpp M4U_PORT_L20_VENC_REF_CHROMA>; + interrupts = ; + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>; + clock-names = "clk_venc_core1"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index d36fcca04cbc..11682659c4c4 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -21,7 +21,6 @@ properties: - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc reg: maxItems: 1